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ASIC Design Methodologies & Tools (Digital) ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions Moderator: Super Moderators		Goto page Previous  1, 2, 3 ... 78, 79, 80 ... 276, 277, 278  Next Jump to page:
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Topics		Replies	Author	Views	Last Post
	Announcement: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!	0	klug	2397	25 Mar 2007 8:41 klug
	false paths and multicycle paths in Digital circuits	8	spartacus2	360	04 Oct 2007 6:50 lakshman.ar
	Need Documents Related to Useful Skew	1	spartanthewarrior	63	04 Oct 2007 5:32 pratap_v
	Bad habit in Verilog HDL	9	cafukarfoo	465	04 Oct 2007 4:38 lubee
	Power estimation tools	20	eexuke	846	04 Oct 2007 1:13 khplnarayana
	glitch detection	5	sam536	300	04 Oct 2007 1:05 khplnarayana
	How to dump 2d arrays in vcd	0	khplnarayana	42	04 Oct 2007 0:28 khplnarayana
	Front-end to Back-end transition	8	master_picengineer	273	03 Oct 2007 14:51 deh_fuhrer
	In what company you are working ?	0	master_picengineer	87	03 Oct 2007 12:27 master_picengineer
	What is Cross-Bar Switch ?	1	suribabut	85	03 Oct 2007 11:44 pouchito
	about formality	3	varkylin	90	03 Oct 2007 10:31 avimit
	Ques.regarding setup fixing?	4	fail1	90	03 Oct 2007 10:29 master_picengineer
	[need]Verilog quickstart! a practical guide by James Lee	1	Guru59	147	03 Oct 2007 9:33 suresh_kvja
	PLZ give attention	3	kumar85sunil	78	03 Oct 2007 9:33 shiv_emf
	STA and primetime	6	mouzid	306	03 Oct 2007 9:30 shiv_emf
	LPE	3	nikhilindia85	99	03 Oct 2007 8:45 sekapr
	synthesis with level shifters	2	stsiligg	90	03 Oct 2007 3:14 sam536
	best and better <Synthesis> tools...<<<>..	21	naaj_ila	510	03 Oct 2007 0:50 andy2000a
	LEC	2	energeticdin	99	02 Oct 2007 18:23 kewlmeanskewl
	design of a ddr sdram controller	3	tinytseng	144	02 Oct 2007 15:55 nemolee
	anybody there to help me.......	5	sandeep.bondada	177	02 Oct 2007 15:37 sandeep.bondada
	Reg: Conformal LEC	0	energeticdin	69	02 Oct 2007 14:55 energeticdin
	counter circuit	0	pas_cktmaker	81	02 Oct 2007 12:07 pas_cktmaker
	Advices	1	master_picengineer	87	02 Oct 2007 10:06 mouzid
	Sequence detector	3	Preddy	168	01 Oct 2007 12:59 onlymusic16
	timin Violations................plz help	9	santoshl	237	01 Oct 2007 11:51 avimit
	2's Complement, is it implemented in Compiler or Hardware	4	tia_design	117	01 Oct 2007 6:23 vlsi_freak
	How to exract spice netlist from layout using SOC Encounter?	1	swgchlry	54	30 Sep 2007 14:34 gliss
	eye diagram	3	master_picengineer	171	30 Sep 2007 14:19 salam2000
	hi	1	andalibneia	120	30 Sep 2007 13:40 jody
	Flip-Flop resolution time and CDC synchronizer	0	gavinsun	108	30 Sep 2007 4:44 gavinsun
	Does anyone have TSMC Reference Flow 7.0 for download?	1	eminem198123	84	30 Sep 2007 3:16 gliss
	vlsi basic n verification related faq's	1	Preddy	105	29 Sep 2007 17:43 hys
	UART DESIGNING >>>I NEED HELP	1	naaj_ila	105	29 Sep 2007 12:48 hys
	VCD file generation in VHDL	2	muni123	135	29 Sep 2007 12:33 hys
	About non-ideal effect of digital system	0	brianguy	54	29 Sep 2007 8:41 brianguy
	Question on using DC command "foreach"	3	aaronhe	51	29 Sep 2007 2:51 aaronhe
	case analysis	2	suribabut	123	29 Sep 2007 2:13 funzero
	Doubt:UART in full duplex mode	6	V	144	28 Sep 2007 16:07 PaulHolland
	Opinion about VLSI Layout Engineer Interview	5	dewabantura	306	28 Sep 2007 14:38 master_picengineer
	Physical design job.	0	prithivikumars	87	28 Sep 2007 13:09 prithivikumars

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