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ASIC Design Methodologies & Tools (Digital) ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions Moderator: Super Moderators		Goto page Previous  1, 2, 3 ... 76, 77, 78 ... 276, 277, 278  Next Jump to page:
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Topics		Replies	Author	Views	Last Post
	Announcement: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!	0	klug	2397	25 Mar 2007 8:41 klug
	Extraction of layout	2	vreddy	102	15 Oct 2007 7:51 xreaver
	smash	7	yaser123	748	15 Oct 2007 5:14 suru
	what is cell delay?and cell delay depends upon what paramets	5	vamsi_addagada	165	13 Oct 2007 2:37 chinnisunny
	Anyone can tell me the difference between VCS and VCS-MX?	4	feel_on_on	177	12 Oct 2007 17:22 sarath51
	interfacing controller, endpoint buffers USB n processor?	1	prashanthaditya	45	12 Oct 2007 14:08 funzero
	Metastable Window.	3	angadir	78	12 Oct 2007 13:55 funzero
	CTS	3	prithivikumars	90	12 Oct 2007 13:40 funzero
	pre route shorts and spacing violations	3	praneshcn	88	12 Oct 2007 13:30 vak
	Pre route DRC checking in Magma design flow	4	chetanbs	153	12 Oct 2007 13:25 vak
	sink vs synchronous	0	pratap_v	51	12 Oct 2007 12:52 pratap_v
	use OPENRISC1200 IP core,......soc?	0	seaman516	60	12 Oct 2007 12:31 seaman516
	Hardware Verification with SystemVerilog	0	mssajwan	78	12 Oct 2007 12:23 mssajwan
	Is it correct-Tri State Logic	0	ship_baba	45	12 Oct 2007 10:47 ship_baba
	AHB/AXI narrow transfers	7	novicevlsi	216	12 Oct 2007 9:41 sree205
	AHB, AXI	5	master_picengineer	156	12 Oct 2007 9:23 novicevlsi
	What is the difference between capture procedure(DFT)?	0	feel_on_on	39	12 Oct 2007 8:53 feel_on_on
	System Verilog	0	kunal1514	78	12 Oct 2007 5:19 kunal1514
	looking for resources on DC,3Q!	0	lubee	39	12 Oct 2007 4:18 lubee
	RTL compiler	2	Preddy	108	12 Oct 2007 4:18 toad
	dftadvisor command for bidi pins	2	carv_13	48	11 Oct 2007 23:04 carv_13
	Free Running Clock???	4	satiah	84	11 Oct 2007 13:46 master_picengineer
	negative edge trigerring vs positive edge trigerring	6	lordsathish	210	11 Oct 2007 12:47 shiv_emf
	Spygalss training materials(Need)	7	sam536	174	11 Oct 2007 7:07 kaustubh
	How to set debu$$fsdb reader version?	1	liuzhili	105	11 Oct 2007 6:17 xuxia
	I/O pads and bi directional pads	2	carv_13	168	10 Oct 2007 23:13 carv_13
	Do anyone do transition test with TetraMax?	1	feel_on_on	63	10 Oct 2007 16:23 dft_guy
	physical design power planning	2	praneshcn	126	10 Oct 2007 16:22 nikhilindia85
	DFT (MENTOR GRAPHICS)	1	gold_2007	86	10 Oct 2007 16:15 dft_guy
	about clock phase	1	pratap_v	99	10 Oct 2007 13:07 master_picengineer
	help!help!help for TIEHI and TIELO!	2	tonyhan1005	153	10 Oct 2007 12:21 au_sun
	VLSI/Computer Architecture, or System School ranking	11	richardleo	383	10 Oct 2007 11:35 richardleo
	Licensing	1	vreddy	87	10 Oct 2007 10:59 master_picengineer
	modelsim error	1	prashanthaditya	210	09 Oct 2007 16:23 gliss
	Synopsys Formality help!	2	heartfree	135	09 Oct 2007 11:29 avimit
	Notch voilation	3	designer_ec	184	09 Oct 2007 11:08 praneshcn
	Passive equalizer + digital amplifier	1	brianguy	83	09 Oct 2007 1:24 sunjimmy
	D5 violation (DFT) MENTOR GRAPHICS	3	gold_2007	94	08 Oct 2007 22:09 dft_guy
	Post Route DRC in Magma	4	chetanbs	152	08 Oct 2007 16:47 chetanbs
	upsizing cells in critical path	3	praneshcn	159	08 Oct 2007 16:46 vak
	multi Vt optimization	2	shavakmm	174	08 Oct 2007 6:29 shavakmm

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