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ASIC Design Methodologies & Tools (Digital) ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions Moderator: Super Moderators		Goto page Previous  1, 2, 3 ... 37, 38, 39 ... 276, 277, 278  Next Jump to page:
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Topics		Replies	Author	Views	Last Post
	Announcement: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!	0	klug	2397	25 Mar 2007 8:41 klug
	How does MOSFET behaves at High frequency?	0	vlsitechnology	57	27 Apr 2008 21:02 vlsitechnology
	Interview questions of cadence	2	vlsitechnology	180	27 Apr 2008 20:44 vlsitechnology
	about dma controller effiency evaluation	0	shield	36	27 Apr 2008 16:44 shield
	Verilog doubts	5	vikas_lakhanpal27	141	27 Apr 2008 15:05 sumit_techkgp
	A good paper on power estimation techniques	1	rz56	105	27 Apr 2008 9:06 ericyuan
	Stick Diagram	1	kumar_eee	33	27 Apr 2008 8:54 ericyuan
	critical path in SRAM	2	kumar_eee	60	27 Apr 2008 8:52 kumar_eee
	Requires .tf and .gds for astro tool	5	mrityunjay_singh_1983	162	27 Apr 2008 8:10 kumar_eee
	NASA has bought Active HDL expert edition	5	gbaerf	273	26 Apr 2008 22:31 ASIC
	Digital questions....can anyone solve these?	4	vlsitechnology	243	26 Apr 2008 22:10 Alkakkali
	VS1011E-S OR VS1011E-L FOR MP3 PLAYER	0	padfooot	78	26 Apr 2008 20:08 padfooot
	regarding cross coverage	2	kishore111281	72	26 Apr 2008 13:19 kishore111281
	Any docs regarding BFM........plz	11	Guru59	524	26 Apr 2008 11:55 simplescalar
	what is the present situation of semiconductor industry	4	pramodm	90	25 Apr 2008 17:56 kumar_eee
	Gilbert Mixer help	2	Foufou	123	25 Apr 2008 14:07 pkmisra
	Using the Clustering Algorithm or H-TREE	0	vamsi_addagada	33	25 Apr 2008 9:48 vamsi_addagada
	Can any one please explain the MAGMA flow from rtl to GDS2.	1	nadellasreedhar	63	25 Apr 2008 9:35 satya_422
	synopsys NanoTime help	2	devop	105	25 Apr 2008 7:10 hemanth
	Verification Questions in Interviews	6	bismillah	258	25 Apr 2008 5:50 shobhitk
	Verilog HDL Samir Palnitkar Book	7	uditkumar1983	402	25 Apr 2008 5:08 akshay.raoy
	buffer cells vs delay cells in delay matching in placement	5	nsreekanthbabu	108	25 Apr 2008 4:58 nsreekanthbabu
	Low Level vs High Level Logic	2	engrbabar	96	25 Apr 2008 4:24 H_D_R
	sdf generated by Astro and PT,any difference?	2	starmx	90	24 Apr 2008 20:41 hemanth
	Description of synopsys library	2	vikramc98406	135	24 Apr 2008 20:29 hemanth
	fishbone and H-tree	3	hfooo1	120	24 Apr 2008 19:09 vlsitechnology
	Digital design Question	6	sp3	231	24 Apr 2008 14:19 the_risk_master
	Need advice regarding NanoSim	0	amsut	33	24 Apr 2008 13:51 amsut
	Number of layers comparison	2	sp3	48	24 Apr 2008 11:15 TonyT
	Floorplanning for multi Vdd designs	3	shavakmm	114	24 Apr 2008 10:42 shavakmm
	USB2.0 , UTMI spec related query	0	senddilu	54	24 Apr 2008 6:56 senddilu
	study material for Moore APACS	0	abhay kulkarni	24	24 Apr 2008 6:12 abhay kulkarni
	need help: verilog book and tool	7	smileysam	162	24 Apr 2008 5:58 muthamil
	cell_rise(fall) rise_transition(fall)	3	hfooo1	153	24 Apr 2008 7:03 hfooo1
	How do I effectively split a bit-string using underscore?	0	kelvin_sg	54	24 Apr 2008 3:22 kelvin_sg
	Hierarchy of SystemC embedded in Verilog	1	gerdemb	57	23 Apr 2008 17:02 xuanzhu
	System Verilog rtl question . . . ! ! !	6	vizpal	144	23 Apr 2008 16:51 xuanzhu
	Elmore model paper	0	carbon9	42	23 Apr 2008 16:44 carbon9
	Scripting Language	6	anishjp	219	23 Apr 2008 11:53 muthamil
	setup and holdtime calculation for a sequential cell Lib	0	muthamil	69	23 Apr 2008 11:37 muthamil
	MAGMA: Placement ISSUE	1	praneshcn	69	23 Apr 2008 10:29 TonyT

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