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ASIC Design Methodologies & Tools (Digital)


ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

tags: asic design, fpga asic, asic company, asic engineer, asic vlsi, asic vhdl, asic dsp, ,
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This topic is locked: you cannot edit posts or make replies. Announcement: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!
 0 klug 3858 25 Mar 2007 8:41
klug
No new posts How to determine Power/Ground Pad number in Chip?
 3 clifftsai 924 13 Dec 2002 2:54
tinybull
No new posts about FPGA Adv 5.3
 1 Vonn 967 11 Dec 2002 3:31
always@smart
No new posts FPGA based BFSK demodulator
 1 Vonn 937 08 Dec 2002 8:34
Vonn
No new posts Modified Booth's Algorithm SHIFTING HOW TO??
 0 gezzas525 804 08 Dec 2002 1:48
gezzas525
No new posts A synthesis problem about Design Compiler
 10 cyteng 2029 05 Dec 2002 13:34
cnz
No new posts I need an FPGA Advantage 5.5 licence file if you can help me
 3 Vonn 1558 02 Dec 2002 9:41
maestor
No new posts Questions about Hardware Simulation Accelerator
 0 john5888 688 02 Dec 2002 5:07
john5888
No new posts study cadence!
 0 cnz 1506 02 Dec 2002 3:26
cnz
No new posts Looking for 1 file from Cadence IC446 ISR CDs
 3 iop3001 1199 02 Dec 2002 2:39
javabean40
No new posts f(at)stchip
 0 zzzzzzzzz 701 29 Nov 2002 17:40
zzzzzzzzz
No new posts Ambit Buildgate feature
 5 nanako 1755 06 Oct 2002 17:17
nanako
No new posts What kind of role the formal verification tool play ?
 3 joe2moon 1132 05 Oct 2002 10:04
Nobody
No new posts CHARGE RECOVERY TECHNIQUES
 0 gezzas525 688 05 Oct 2002 2:52
gezzas525
No new posts Request for VeRiLOG E-books or links...
 7 always@smart 2032 02 Oct 2002 23:17
coppervaporlaser
No new posts What can I do if I doubt about chip damaged by ESD?
 2 etrobin 1043 02 Oct 2002 23:00
coppervaporlaser
No new posts What is ASSP?
 2 mami_hacky 1036 02 Oct 2002 22:51
coppervaporlaser
No new posts Which is the best commercial verilog simulator?
 8 frankta 1673 02 Oct 2002 18:02
mdlin
No new posts Tools from artwork
 0 cdic 494 01 Oct 2002 20:14
cdic
No new posts 200MHz DDR Memory controller
 11 mami_hacky 2644 30 Sep 2002 17:51
mami_hacky
No new posts [ Poll ] SystemVerilog
 3 thecat 1150 27 Sep 2002 4:05
joe2moon
No new posts How can i balance the clock latency in different gated clock
 5 Nobody 1772 27 Sep 2002 3:59
seasonyangd
No new posts ere
 0 lilzz 645 27 Sep 2002 3:12
lilzz
No new posts verilog simulation question
 4 floatgrass 1303 26 Sep 2002 23:49
andromeda
No new posts Which StandCell Library include Integrated gate-clock cell ?
 7 S0933263236 1017 26 Sep 2002 23:09
andromeda
No new posts can this verilog description be synthesized?
 7 Rainboww 2016 26 Sep 2002 22:42
andromeda
No new posts Anybody would share cadence ic design software?
 1 syncmaster 958 24 Sep 2002 0:05
jourval
No new posts LPM_FIFO_DC!!
 4 ramo 1107 23 Sep 2002 15:14
ramo
No new posts With embedded DesignTime in DC, why still Primetime ?
 1 joe2moon 955 20 Sep 2002 11:55
czhomo
No new posts Need Fpga Compiler
 3 ramo 1108 18 Sep 2002 17:08
ramo
No new posts @ltera Max II and qu(at)rtus - help with tools needed!
 1 ted 1114 17 Sep 2002 15:54
ngjh
No new posts AC Supply / Contactless Smart Card
 3 ASIC 831 17 Sep 2002 6:01
napong
No new posts Already have FPGA compiler, why need Design Compiler (DC)?
 13 dd2001 2783 16 Sep 2002 14:02
joe2moon
No new posts Anybody Help Me
 0 shockstar 780 16 Sep 2002 5:31
shockstar
No new posts could someone advice me when design from .35u to .25u ?
 3 etrobin 1078 16 Sep 2002 2:36
asicplace
No new posts DDR FCRAM vs DDR SDRAM
 0 mami_hacky 845 15 Sep 2002 11:14
mami_hacky
No new posts Solidify
 0 eziggurat 626 14 Sep 2002 6:38
eziggurat
No new posts Help for verific(at)tion n(at)vig(at)tor
 0 mdlsn 595 13 Sep 2002 19:17
mdlsn
No new posts Negative hold time
 7 magicball 1210 12 Sep 2002 14:56
steak
No new posts Where Can I find Windows CE.NET 4.0 or Higher?
 0 GeorgeYu 606 11 Sep 2002 12:16
GeorgeYu
No new posts fpga to asic convertion--help
 1 ramo 678 11 Sep 2002 6:31
cyteng
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