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ASIC Design Methodologies & Tools (Digital) ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions Moderator: Super Moderators		Goto page Previous  1, 2, 3, 4, 5 ... 276, 277, 278  Next Jump to page:
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Topics		Replies	Author	Views	Last Post
	Announcement: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!	0	klug	2397	25 Mar 2007 8:41 klug
	SWP (Single Wire Protocol)	0	sunilbudumuru	69	08 Nov 2008 6:16 sunilbudumuru
	what is metal fill lines connected to?	1	dazzling_deepika	72	07 Nov 2008 21:36 Old Nick
	Need a State Diagram Editor?	0	DonnaMitchell	33	07 Nov 2008 18:25 DonnaMitchell
	Comparison between results of Prime Power & Power Compil	0	win3y	27	07 Nov 2008 9:24 win3y
	Hot carrier check?	0	ac123	51	07 Nov 2008 6:53 ac123
	flip flop basic question	2	darklord4	111	07 Nov 2008 6:39 darklord4
	free synthesis tool	3	adilkhan123	90	06 Nov 2008 15:32 dexter_ex_2ks
	How to integrate Specman Elite with Ncsim Simulator	0	navakrishnn	21	06 Nov 2008 11:43 navakrishnn
	How to design a CML RS-latch?	0	alard	30	05 Nov 2008 23:24 alard
	TSMC Library	15	Hards	1656	05 Nov 2008 19:38 samenmohammad
	different of libraries	3	samenmohammad	141	05 Nov 2008 19:01 samenmohammad
	Leonardo spectrum	3	sandeep_sggs	132	05 Nov 2008 19:00 samenmohammad
	possible convert .db to .syn or .lib	3	samenmohammad	87	05 Nov 2008 18:59 samenmohammad
	who can tell me how to convert dc scripts	2	HolySaint	60	05 Nov 2008 12:43 HolySaint
	talk about power on sequence	0	archillios	48	05 Nov 2008 11:59 archillios
	how to compile sysetem verilog file using cadence tools	1	mallikmarasu	51	05 Nov 2008 10:28 ljxpjpjljx
	Avoid bit-blast I/O ports on Synopsys synthesis	4	solvall	192	05 Nov 2008 8:19 frankaurora
	Board Design Eng. - How To Start ?	2	barnea10	78	04 Nov 2008 18:57 jvish
	EDT TestKompress K19 violation	1	shakti_pattnaik	30	04 Nov 2008 16:48 vikram161
	DFT	2	ciocco	126	04 Nov 2008 8:59 ciocco
	how the clock latency influences timing in the STA	3	owen_li	123	04 Nov 2008 6:20 crtran
	a question on .synopsys_dc.setup file	3	larosar	84	03 Nov 2008 16:35 dcreddy1980
	Please help me temperature sensor	0	psthanh	42	03 Nov 2008 16:11 psthanh
	Synopsys AstroRail	0	kowada	33	03 Nov 2008 13:58 kowada
	Doubt in system verilog	6	deepu_s_s	210	03 Nov 2008 12:04 satishkumar
	Hi, im new in laker. pls help.	0	wccheok	54	03 Nov 2008 7:44 wccheok
	Cadence ETS timing report file: Other End Arrival Time	0	no_mad	36	03 Nov 2008 3:24 no_mad
	Anyone has tutorials for Astro?	19	eruisi	984	02 Nov 2008 10:25 jawa527
	Anybody has document on ASIC flow with ASTRO	20	satyakumar	867	02 Nov 2008 5:02 jawa527
	CUP - circuit under pad	3	hiral.kotak	198	01 Nov 2008 18:44 sunjimmy
	soc design order' problem	4	HolySaint	84	01 Nov 2008 16:16 santhosh007
	synthesis with design compiler	0	cosmonutt	75	01 Nov 2008 9:11 cosmonutt
	New in Digital design and synthesis...some questions I have.	5	dexter_ex_2ks	210	31 Oct 2008 12:15 santhosh007
	TANNER EDA Tool	0	avg_emp	57	31 Oct 2008 9:52 avg_emp
	Voltage and cell delay of a cell (STA)	6	angadir	249	31 Oct 2008 6:16 Anbusivam
	Why Layout have more ports than source when doing LVS?	6	swgchlry	204	30 Oct 2008 13:16 mnluan
	Launch and capture in At-speed mode	5	kiranks9	195	30 Oct 2008 7:23 santhosh007
	How to disable the "Simulation time progresses" in	1	hgby2209	36	30 Oct 2008 7:00 santhosh007
	galois field multiplier	0	leongch	45	30 Oct 2008 6:29 leongch
	Hi, I'm very new in verification, have some questions...	2	dexter_ex_2ks	105	29 Oct 2008 14:45 dexter_ex_2ks

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