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ASIC Design Methodologies & Tools (Digital)


ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

tags: asic design, fpga asic, asic company, asic engineer, asic vlsi, asic vhdl, asic dsp, ,
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This topic is locked: you cannot edit posts or make replies. Announcement: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!
 0 klug 3864 25 Mar 2007 8:41
klug
No new posts how to creat work lib in m(at)gm@
 1 nozone 805 17 Nov 2003 22:35
nozone
This topic is locked: you cannot edit posts or make replies. $ynOpsys version 2003.09 released??
 10 srisrisri 1894 17 Nov 2003 11:32
windflower
No new posts PCB Design Rules
 3 EDALearner 566 17 Nov 2003 1:07
phonedrop
No new posts DFT
 0 qpskguy 409 16 Nov 2003 12:37
qpskguy
No new posts SMD Package Naming Rule
 1 EDALearner 497 14 Nov 2003 21:47
flatulent
No new posts FREE tools for analog and mixed signal design
 0 pankaj 438 14 Nov 2003 13:42
pankaj
No new posts I2C slaver IP
 2 coolaron 759 14 Nov 2003 2:20
niko_zhang
No new posts Verilog to Spice ?
 12 joe_chuang 2890 13 Nov 2003 19:08
xtecer
No new posts Difference between TimeMill & StarSim
 3 crystal 964 13 Nov 2003 1:16
linuxluo
No new posts DFT info??
 3 jelydonut 1066 12 Nov 2003 8:23
crystal
No new posts CoreConsultant online reference
 0 crystal 344 12 Nov 2003 8:06
crystal
No new posts how to run star-rcxt with multi-cpu
 1 chyau 457 07 Nov 2003 7:07
carrie
No new posts MOS low or nul VT voltage threshold for analog
 3 okguy 434 07 Nov 2003 3:40
goodboy_pl
No new posts how IC are implementing PLL to increase the onchip frequency
 4 intel 914 07 Nov 2003 0:32
khouly
No new posts [Astro] Why core Down?
 8 Wang Chin 1585 06 Nov 2003 11:16
gerryhsu
No new posts Does anyone know the IC5033?
 1 lyw7252 908 06 Nov 2003 11:14
gerryhsu
No new posts help for nc-verilog
 1 Aigneryu 1271 05 Nov 2003 12:39
aramis
No new posts How to use Hercules to translate gdsII into milkyway?
 4 mike_bihan 1825 04 Nov 2003 18:50
chyau
No new posts How to create FRAM view in Astro
 1 nanako 1523 04 Nov 2003 18:44
chyau
No new posts f(at)stsc(at)n and fl*xt*st
 1 tonyo_guy 696 03 Nov 2003 2:52
z81203
No new posts strange problem of DC
 3 fantaci 848 02 Nov 2003 4:15
cnz
No new posts Which ASIC Vendor has 32 bit CPU and 80 MHZ DAC
 2 john5888 394 31 Oct 2003 19:40
john5888
No new posts A M S 3.51 Hit Kit challenging problem
 0 godz 559 31 Oct 2003 14:51
godz
No new posts input capacitance
 1 taoly 720 31 Oct 2003 9:39
Humungus
No new posts how to do a scan chain in Astro?
 9 Wang Chin 1526 31 Oct 2003 8:45
cikyen
No new posts Clock-Tree Extraction/Analysis Tools...
 5 joe2moon 1480 31 Oct 2003 7:05
kfy
No new posts TTL to Diffential TTL
 0 tungchang 601 31 Oct 2003 0:29
tungchang
No new posts C(at)dence SE DSM
 0 tonyo_guy 616 31 Oct 2003 0:21
tonyo_guy
No new posts Chip Implement flow
 14 zackwang 2436 30 Oct 2003 20:25
cdic
No new posts DC only read VHDL
 1 RFID 922 29 Oct 2003 17:21
roli
No new posts Vera
 4 saho 880 29 Oct 2003 7:28
crystal
No new posts I/O circuits design
 1 taoly 549 28 Oct 2003 8:19
cedance
No new posts wanted cell characterization tools
 2 mars64 845 27 Oct 2003 0:50
pookey
No new posts cds_orcad_PSD
 0 visualart 550 26 Oct 2003 5:05
visualart
No new posts How run the synps?
 11 visualart 1839 24 Oct 2003 6:30
visualart
No new posts sdfannotate error?
 1 xiongdh 870 23 Oct 2003 3:48
philewar
No new posts Weighted Round Robin
 1 CRiSP 773 22 Oct 2003 8:31
mami_hacky
No new posts how generate netlist with "ripper" in cad*ence
 0 xiongdh 500 22 Oct 2003 7:30
xiongdh
No new posts Spartan-IIELC Development Board.
 0 senthilkumar 619 21 Oct 2003 12:17
senthilkumar
This topic is locked: you cannot edit posts or make replies. [Help] Could NCverilog run many testbench in sequence?
 0 syncom 602 21 Oct 2003 8:36
syncom
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