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ASIC Design Methodologies & Tools (Digital)
ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions
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This topic is locked: you cannot edit posts or make replies. Announcement: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!
 0 klug 2397 25 Mar 2007 8:41
klug
No new posts Vhdl --> VLSİ
 2 myertas 359 16 Jan 2003 12:01
linuxluo
No new posts how do I fix glitches?
 9 ramo 773 16 Jan 2003 10:01
yingyang
No new posts Modelsim 5.7a released
 3 leonqin 899 16 Jan 2003 6:44
ntxp
No new posts on chip bus arbitration protocols
 0 patchquinn 296 15 Jan 2003 16:23
patchquinn
No new posts Behavioral Synthesis tools for FPGAs?
 1 Ohh 283 15 Jan 2003 13:39
geconom
No new posts How to simulate Post-P&R?
 4 blankcd 489 15 Jan 2003 9:32
ljkong
No new posts How to perform post-synthesis sim with synplify results?
 4 snakebites 515 15 Jan 2003 9:26
ljkong
This topic is locked: you cannot edit posts or make replies. Where is the "active topic " menu
 1 LLCD 338 14 Jan 2003 17:00
tjalps
No new posts Micro UART CORE
 0 Aircraft Maniac 396 14 Jan 2003 10:48
Aircraft Maniac
No new posts free Evaluation RISC
 0 Al Farouk 341 14 Jan 2003 7:52
Al Farouk
No new posts 32 bit ALU doubt
 6 eda_wiz 828 14 Jan 2003 5:55
uil
No new posts What's the speed grade for FPGA?
 4 snakebites 913 10 Jan 2003 21:20
efundas
No new posts Specman
 1 Joyee 763 10 Jan 2003 12:07
windflower
No new posts [req] sw to program x_i_l_i_n_x x_c_9_5_1_0_8
 1 thomaz 587 10 Jan 2003 8:06
Bartart
No new posts sugar
 0 hong_vito 516 09 Jan 2003 7:16
hong_vito
No new posts how to use P&R data?
 3 xworld2008 813 08 Jan 2003 12:36
linuxluo
No new posts 8(at)486 System Architecture 3rd
 2 freexyz 801 08 Jan 2003 12:30
linuxluo
This topic is locked: you cannot edit posts or make replies. RTL Synthesis & Static Timing analysis presentation
 4 avinashr 1700 07 Jan 2003 19:26
gold_kiss
No new posts How to?Power Calculations in Efficient Charge Recovery Logic
 0 gezzas525 480 07 Jan 2003 13:33
gezzas525
No new posts Where can I download free USB 1.0 IP?(verilog is better )
 2 fengbj 761 07 Jan 2003 7:55
jazz
No new posts estimate clock tree delay
 4 kinysh 988 05 Jan 2003 23:08
papertiger
No new posts ASIC Design, file extention flow!
 0 mami_hacky 665 05 Jan 2003 6:05
mami_hacky
No new posts Using DC to synthesis twice??
 17 swchen2002 2147 04 Jan 2003 15:29
linuxluo
No new posts Verification tools
 20 mami_hacky 4027 03 Jan 2003 3:21
hong_vito
No new posts Proteus and PIC16F628
 2 isabelino 573 02 Jan 2003 23:05
sick_man
No new posts Compare FPGA CompilerII3.7 with Synplicity Amplify3.1 ?
 11 fbiair 2141 02 Jan 2003 20:22
Gunship
No new posts P*otel nVisage, aldec and Modelsim?????
 1 synq 686 02 Jan 2003 18:13
sparkytron
This topic is locked: you cannot edit posts or make replies. Actel Libero Design Environment V2.2 Full License
 0 cssheu 691 02 Jan 2003 16:54
cssheu
This topic is locked: you cannot edit posts or make replies. Looking for E*F*A*L*i*c*g*e*n
 0 l_z_h 930 02 Jan 2003 2:34
l_z_h
No new posts How to generate the libpli.dll for NC-Desktop ?
 7 joe2moon 1498 01 Jan 2003 16:07
joe2moon
No new posts FREE MATERIAL FOR VLSI AND EMBEDDED SYSTEMS
 3 Vonn 975 01 Jan 2003 16:06
hch16550
This topic is locked: you cannot edit posts or make replies. Looking for EFALicgen
 0 bhneclzh 1791 01 Jan 2003 11:45
sigmaxyz
No new posts Good Link for Analog Bipolar IC Design
 3 steve88 1098 31 Dec 2002 13:02
juggernaut7
No new posts IC station "Asking"
 1 Vonn 658 31 Dec 2002 10:35
ejean
No new posts 8088 or 8086 Coreware
 0 jelydonut 611 30 Dec 2002 22:02
jelydonut
No new posts checklist for successful synthesis
 4 vsop 1119 29 Dec 2002 11:54
linuxluo
No new posts clock tree/reset tree
 7 openwindows 828 29 Dec 2002 9:52
roli
No new posts Timemill & Powermill
 10 cyteng 2301 29 Dec 2002 5:38
edaguy69
No new posts I want PowerPc 603e functional model
 0 linuxluo 716 29 Dec 2002 4:23
linuxluo
No new posts I am a newer to synopsys DC,where can find some tutorial?
 23 gxcr 2770 28 Dec 2002 12:26
ChipCrack
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