kcinimod
Member level 3
Hi all,
i am currently using the virtex-5 FPGA from xilinx. with its GTP transceiver i configure in the coregen to generate a simple SIPO register and i wanted to simulate the function using ISim. the clkin to the shared pma pll is driven through an IBUFDS from a differential external clock. i have also input a periodic differential input. However, when i ran the simulation, the PLLLKDET and the parallel data to the FPGA had no values. i am not sure what went wrong with the testbench or configuration. would appreciate it if anyone could guide me along.
i am currently using the virtex-5 FPGA from xilinx. with its GTP transceiver i configure in the coregen to generate a simple SIPO register and i wanted to simulate the function using ISim. the clkin to the shared pma pll is driven through an IBUFDS from a differential external clock. i have also input a periodic differential input. However, when i ran the simulation, the PLLLKDET and the parallel data to the FPGA had no values. i am not sure what went wrong with the testbench or configuration. would appreciate it if anyone could guide me along.
