Working on one signal, but reading input on another

[timsanr]

Hi,

what to do in situation when I have FSM, which works on rising edge of clock, and I need to read incoming signal on some port on rising edge of another signal (I generate it inside)? I can't do it in that FSM with rising_edge() on that another signal because of 'bad synchronous description...'.
Could yo help, give some tip how to do it? Second process is good solution?

 

[TrickyDicky]

You dont. You have everything using the rising edge of one single clock.
If you are generating lots of clock (ie using rising_edges) you are doing it wrong. You should generate clock enables instead. You should not use any old signal's rising edge.

 

[FvM]

A signal originated from an unrelated clock domain should be double registered to the FSM clock before used as an input. Additional precautions must be taken to achieve consistent domain transfer of multibit signals.

 

[timsanr]

1. After reading about that clock enable, is it one clock width impulse? And I should generate it in appropriate moments and as often as I need to read that external signal? And then I should check level of that CE signal (CE = '1') not the rising edge?

2. If I know exactly the moment of transition from 0 to 1 of my internal signal. And that signal rising edge causes that data appears on input pin, shoudn't be enough that I will read data there where I set 1 to that signal?
e.g.

strobe_data <= '1'; -- previous value = 0
data_loc <= data_input;