Why the net In1 in this layout is incomplete?

[Shlapenka]

Incomplete net

Hi all,

So here is my problem: i designed a circuit and now doing a layout. The layout is complete, has no DRC errors but there is a problem. In Fig.1 i am showing the part of layout that has a input In1, ant it is connected to PMOS transistors trough net named In1 (bright white collor):

Fig.1:

**broken link removed**

And here is the layout:

Fig.2:

**broken link removed**

So as i said there is no DRC errors, but it says that net In1 in the layout is incomplete. What i have done wrong? As i can see i connected everything as in schematic. Thank you very much for help!

 

[wpchan05]

Re: Incomplete net

did you label the net as In1 by using the right layer?

 

[Shlapenka]

Re: Incomplete net

In schematic it was named In1 automaticly, in layout it was also named in1 after connecting transistors, ntap and In1 pin. (text in green in layout pic is added by me, it is not shown in layout i added it with MS paint).

Pin was metal1 layer, connections to it are made by same metal1 layer.

 

[erikl]

Re: Incomplete net

In Fig.1 i am showing the part of layout that has a input In1, ant it is connected to PMOS transistors trough net named In1 (bright white collor):

... it says that net In1 in the layout is incomplete.

It is incomplete, because In1 isn't connected to vdd! or to a pin. You must either connect it to vdd! (or how your pos. pwr supply is called), or put a metal1 pin over it.

 

[Shlapenka]

Re: Incomplete net

it is conned to In1 pin, it is that big rectangle in top. That pin was generated from schematic as was generated all other pins and devices..

 

[erikl]

Re: Incomplete net

it is conned to In1 pin, it is that big rectangle in top. That pin was generated from schematic as was generated all other pins and devices..

It's only a valid pin, if a metal1 pin layer is put over the metal1 drawing layer. Make sure it is ("t" = tap). Is it?

 

[Shlapenka]

Re: Incomplete net

yes everything is as u said here is the pic:

**broken link removed**

it is a picture of generated connections.

Added after 35 minutes:

Solved my problem! Looks like it wa problem with my ntap's. I had created them myself and it seems something was wrong with them, even they passed drc. I deleted them and replaced them with via's M1_NWELL (metal1 to nwell). Now the net is complete and seems that layoth again has no drc errors.

Few toughs tho, metal1 to nwell are same as ntap right? And to save layout space it would be better maby to use ntap guardrings?

 

[erikl]

Re: Incomplete net

Solved my problem! Looks like it wa problem with my ntap's. I had created them myself and it seems something was wrong with them, even they passed drc. I deleted them and replaced them with via's M1_NWELL (metal1 to nwell).

So I followed the wrong trail: your design system seemingly doesn't need the pin layer (this is different from PDK to PDK). Sorry! And thanks for your feedBack!

Few toughs tho, metal1 to nwell are same as ntap right?

Not quite: ntap is just the necessary N+ implant in the n-well to guarantee a low-resistive contact to the well. The metal1 connection over the ntap is necessary to allow for a connection to VDD, which is obligatory. That's why this net was incomplete before. (Unfortunately the missing ntap to metal1 connection wasn't easily recognizible from your layout image.)

And to save layout space it would be better maby to use ntap guardrings?

I don't think you will save space by using guardRings because they need extra space; they are always a good idea, however, for good bulk contact, isolation from other devices and from noise. If you have enough space, use guardRing(s), for ntap as well as for ptap. Use as many contacts (incl. metal1) as possible.