[SOLVED] Why State machines are preferred ?

[verylsi]

Hello All,

I have some doubts regarding state machine implementation in VHDL.

State machines are faster and are considered as a better coding technique.
I want to know then what makes state machines better than a simple if-else or case logic?

Is it because of its encoding techniques?
or are the synthesized differently in FPGAs than other logics ?
please throw some light on it.

Thanks in advance..

 

[TrickyDicky]

Bad state machines would be worse than well written code without vhdl coded state machines. And vice-versa
It has nothing to do with speed or better coding technique. Bad code is bad code.

I dont know where you get the idea that state machines are "faster" - faster than what?

At the end of the day, its just a load of LUTs and registers in an FPGA, however you code. But Id rather have it easier to read than get a 2% fmax increase.

 

[mohi@608]

well the state machine gives the programmer an idea of how the chip would behave in different states and it would be very helpful in any HDL coding...