Why does a=a+b that works in CPP not work the same CPP in Verilog???

[stackprogramer]

Why does the a=a+b expression that works in CPP not work the same CPP in Verilog???
when I used a=a+b; the expression, the last value of a reg is not summed with b, the result return b not a+b in Verilog...
How can implement a=a+b with at least resource in FPGA

Thanks in advance

 

[KlausST]

Hi,

I guess it does work, but ..... verilog code is processed in parallel where the result is visible one clock later.
Verilog is not software that is processed line after line.

If you need more details, then
* show your code
* tell what you expect
* and what you see instead

Klaus

 

[danadakk]

Why does the a=a+b expression that works in CPP not work the same CPP in Verilog???
when I used a=a+b; the expression, the last value of a reg is not summed with b, the result return b not a+b in Verilog...
How can implement a=a+b with at least resource in FPGA

Thanks in advance

Post your whole module code....

Regards, Dana.

 

[stackprogramer]

Thanks very much @KlausST
@danadakk, This is my Verilog code:

module test_core
  #(parameter WIDTH=16)
   (input clk, input reset);
   reg [15:0] a;
   reg [15:0] b;
   reg [15:0] k;
   initial begin
       a=0;
       b=0;
       k=0;
   end
   always @(posedge clk) begin
      for (k = 0; k < 5; k = k + 1)
      {
       b=i;
       a=a+b;
    
      $display("-------Clock is triggerted...%0d ----",a);
      }
   end
 
 
endmodule //

In Verilog test bench print a reg value according to below:

-------Clock is triggerted...0 ----
-------Clock is triggerted...1 ----
-------Clock is triggerted...2 ----
-------Clock is triggerted...3 ----
-------Clock is triggerted...4 ----

But I expect this result:

-------Clock is triggerted...0 ----
-------Clock is triggerted...1 ----
-------Clock is triggerted...3 ----
-------Clock is triggerted...6 ----
-------Clock is triggerted...10 ----

 

[danadakk]

always @(posedge clk) begin
for (k = 0; k < 5; k = k + 1)
{
b=i;
a=a+b;

$display("-------Clock is triggerted...%0d ----",a);
}
end

should not b = i be b = k ?

Why do you expect result to inc by +2 ? It should inc by k ?


Regards, Dana.

 

[stackprogramer]

should not b = i be b = k ?

Why do you expect result to inc by +2 ?


Regards, Dana.

I'm sorry, It is a typo, But in my project is b=k;

module test_core
  #(parameter WIDTH=16)
   (input clk, input reset);
   reg [15:0] a;
   reg [15:0] b;
   reg [15:0] k;
   initial begin
       a=0;
       b=0;
       k=0;
   end
   always @(posedge clk) begin
      for (k = 0; k < 5; k = k + 1)
      {
       b=k;
       a=a+b;
    
      $display("-------Clock is triggerted...%0d ----",a);
      }
   end
 
 
endmodule //

 

[ads-ee]

This is Verilog, a Hardware Description Language, and for loops behave differently than in SW.

A for loop is completely unrolled and creates a parallel implementation of what is inside the for loop.

i.e. your for loop is equivalent to

---

Code Verilog - [expand]
1
2
3
4
5
6
7
always @(posedge  clk) begin
  a=a+0;
  a=a+1;
  a=a+2;
  a=a+3;
  a=a+4;
end

---

Synthesizing this code will result in only a=a+4 as the input to a register.

You are also using blocking assignments (again) in a edge sensitive always block where you should be using non-blocking assignments.
See:
https://www.edaboard.com/threads/difference-between-blocking-and-nonblocking-in-verilog.320869/
https://www.sutherland-hdl.com/papers/1996-CUG-presentation_nonblocking_assigns.pdf