[SOLVED] When do we call that 2 clocks are not synchronized?

[VuTang]

Dear all,

Please help me answer question below:
Assuming that we have two clock signals: clk1 and clk2, when do we call that clk1 and clk2 are not synchronized?

Thank you very much.

 

[K-J]

Assuming that we have two clock signals: clk1 and clk2, when do we call that clk1 and clk2 are not synchronized?

When they originate from different sources.

Kevin

 

[shaiko]

When they originate from different sources.

It may also happen when 2 clock nets originate from the same source but arrive to the destination logic after travelling significantly different length.
In that case, the different propagation delay causes a skew between clocks.

 

[TrickyDicky]

It may also happen when 2 clock nets originate from the same source but arrive to the destination logic after travelling significantly different length.
In that case, the different propagation delay causes a skew between clocks.

But here they would still be synchronised but out of phase.

 

[slutarius]

Assuming that we have two clock signals: clk1 and clk2, when do we call that clk1 and clk2 are not synchronized?

Most of working clocks are from PLL output or directly clock supply. And then, they can be divided into slower clock via FF.
If clk1, clk2 are not originated from same PLL output or clock supply, they are considered to be asynchronized to each other.

If you are working with internal module or design and clk1 and clk2 are inputs, please check with clock supply designer or design specification to see where they were created.

 

[VuTang]

Thank you for your help.
After reading your answers above, I come to a conclusion:
"If clk1, clk2 are not created by a same source, they will be considered as 2 asynchronized clocks."
But, something is not really clear:
1. If clk1 and clk2 come from same source, but have diference period, are they synchronous? For example: clk1 period is 100 MHz and clk2 period is 200MHz but come from a PLL or MMCM.
2. If clk1 and clk2 come from deference sources but have same period, are they synchronous?

 

[FvM]

The first question has been discussed in this recent thread. https://www.edaboard.com/threads/349892/
The clocks are basically synchronous, but if the frequency according to the common multiple is too high, it might be necessary to treat them as asynchronous.

The second question was already answered by yourself.

If clk1, clk2 are not created by a same source, they will be considered as 2 asynchronized clocks.

 

[TrickyDicky]

2. If clk1 and clk2 come from deference sources but have same period, are they synchronous?

Just to explain why: the two different sources will have slight differences in actual clock. two crystals that claim to be Xmhz will actual have a specified ppm (parts per million) variation. So the two sources will slowly drift over time relative to each other.

 

[andre_luis]

Generally speaking, in addition to the Delay caused by the propagation at the transmission line, as well as variations of crystals themselves, I would add the random jitter as another factor that characterizes the clocks as synchronous or asynchronous. To better determine how to categorize whether are synchronous or asynchronous, this will depend on the clock frequency compared to the static and dynamic characteristics of the circuit.

 

[slutarius]

The clocks are basically synchronous, but if the frequency according to the common multiple is too high, it might be necessary to treat them as asynchronous.

Just a comment.
That is the way of EDA tools when they judge the clock issue from a design. Sometimes, clock periods in back-end flow will have their own margins, and the margin is varied depends on periods. in those cases, common multiplies of synchronous clocks are also too high.