what will the following verilog code generate?

[shivams]

always@*
begin
if en
y=a;
else
z=b;
end

 

[ninaleiqi]

its a selector

 

[shivams]

by selector u mean mux? but code has 2 outputs

 

[ninaleiqi]

if en what's z's value. and if not ,what's y's value, it is not complete?

Added after 8 minutes:

u can try it through Quartus RTL viewer.

 

[shitansh]

always@*
begin
if en
y=a;
else
z=b;
end

This will infer a latch for y and z,

e.g.
always @*
begin
if (en)
y = a;
end

always @*
begin
if (~en)
z = b;
end

HTH