what is diff b/w reg [0:2] and reg [2:0]

[moonnightingale]

Can any body explain me the difference between these two verilog commands,kindly tell me with some example

reg [0:2] address
reg [2:0] address

 

[hareshcooleng]

it is the vector u return that [2:0] it means MSB is 2 and LSB is 0. so reg [2:0] address is saving some particular value at the parameter we assign their.and also the same meaning for other date [0:2] it MSB 0 and LSB 2.

 

[Chops211]

This is important because different systems use different Endianness (which this issue is called).

 

[moonnightingale]

kindly give some small example for this

 

[Sink0]

Its the order that the system will write the bits on the regs... lets says the number 3 it would be written as 011 or as 110.

 

[permute]

The best example I can give is looking at lists vs numbers. eg
list:
add r0 r1 r2
or r2 r1 r0
bra X

number:
1024

if i asked for instruction[0], what would it be? what about digit[0]?

for lists, or things that represent lists, its nice to have a 0, 1, 2, 3 ordering.
for numbers, its often nice to have a 3, 2, 1, 0 ordering. eg digit[0] is the lsb, digit[3] is the msb.