J90
Junior Member level 1
Hi there,
I'm designing a VGA signal generator. I'm actually stuck into the design of the RAM interface. The RAM should contain the data that has to be put on the screen by the signal generator.
The signal generator requires (should it?) a continuous access to the RAM, this because the screen is continuously refreshed. As a consequence the address bus of that ram is constantly driven by the signal generator.
So, if my component continuously access to the RAM, keeping the address bus busy, how is one supposed to write data into that RAM?
Looking on the internet trying to find some examples I got this:
Looks like the device simply puts the desired address on TEXT_A and reads the corresponding data through TEXT_D. Ok, fair enough, but ...
How is it possible to write to the same RAM if this is being kept busy by that signal generator?
Does this requires a particular RAM (maybe with 2 separate pairs of buses) ?
Is it possible to interface this model (which requires a constant access to the RAM) with an external RAM like a DDR one?
Thank you for your time already.
I'm designing a VGA signal generator. I'm actually stuck into the design of the RAM interface. The RAM should contain the data that has to be put on the screen by the signal generator.
The signal generator requires (should it?) a continuous access to the RAM, this because the screen is continuously refreshed. As a consequence the address bus of that ram is constantly driven by the signal generator.
So, if my component continuously access to the RAM, keeping the address bus busy, how is one supposed to write data into that RAM?
Looking on the internet trying to find some examples I got this:
Code:
entity vga80x40 is
port (
......
TEXT_A : out std_logic_vector(11 downto 0); -- text buffer
TEXT_D : in std_logic_vector(07 downto 0);
......
);
end vga80x40;
Looks like the device simply puts the desired address on TEXT_A and reads the corresponding data through TEXT_D. Ok, fair enough, but ...
How is it possible to write to the same RAM if this is being kept busy by that signal generator?
Does this requires a particular RAM (maybe with 2 separate pairs of buses) ?
Is it possible to interface this model (which requires a constant access to the RAM) with an external RAM like a DDR one?
Thank you for your time already.