verilog code, please rectify errors

[viswanath404]

Verilog Code for floating point adder:
Procedure for this stage:
Take the Two 7-bit exponential binary numbers (a and b) and subtracting them. Let the result be named as ‘ediff’. We have to shift (logical right shift) the mantissa of the second number (f2 10digits) based on the ‘ediff’. HERE WE HAVE TO CONSIDER THE HIDDEN BIT IN THE EXPONENTIAL NUMBER.
My Code:
module shifting(a,b,f2,f2_result );
input [6:0]a;
input [6:0]b;
input [9:0]f2;
output [10:0]f2_result;
reg [10:0]f2_var;
wire [6:0]ediff,ediff_var;
assign ediff[6:0]=a[6:0]-b[6:0];
assign ediff_var[6:0] = ediff[6:0];
assign f2_var=f2[10:0];
integer i;
wire [7:0]zero_8;
always @ (i)
begin
for(i=1;i>=10;i=i+1)
begin
if(ediff_var>zero_8)
begin
f2_var[9:0]=f2_var[10:1];
f2_var[10]=1'b0;
ediff_var=ediff_var-1'b1;
end
end
end
assign f2_result[10:0]=f2_var;
endmodule