Verilog Code PLEASE HELP!!!!!!!!!!!!!

[ntropy]

I need help displaying the duty cycle of an incoming 1 MHz signal. The output number will be displayed as a hex value/ascii number. Please help!!

For back information, I'm using a Spartan 601 starter kit board. With the use of the provided base reference design interface there is a second tab that has a user defined section. The user is allow to select control bits (8 bits). The goal is to be able to select control bit 0000 0001 and select send and have the desired duty cycle channel to be displayed. The goal is to have ten channels that I can monitor the duty cycle.

 

[Umair_ali]

First you need to determine the frequency on which ur design will run... i.e. suppose u are using 50Mhz..... it means that maximum sample rate for your desired signal (which is 1Mhz) is 50...... so the duty cycle can have the range from 0-50.... the task is quite simple, sample your up coming signal and then decide for how many times the signal is high..... and you get the desired result.... and for n-channels... simply replicate the code n times..... calculating duty cycle for each channel separately but output only the selected control bit..................................... I will upload the code.... Very soon.

Hope You Helped!!!

 

[aftermorning]

Umair_ali gets the point and i think you can upconvert the main clock with the DCM. then the accuracy performance will be better.

 

[ntropy]

Thank you Umair_ali for your help. It is greatly appreciated. I'm using a 50 MHz clk signal, however I would like a range of 0-100% to be displayed for each channel--maybe I misunderstood what you were saying. I hope that you can post your code and we can work this out. I'm waiting for your reply for I'm stuggling with this problem. Thank you once again for your help .