ucf timing constraints

[lokesh_boddu]

Hi

i have a question on timing constraints

1. How will find out the setup and hold time of a FF before hand?
2. How I know that multi cycle path exist between two FFs?
3. How to find Clock frequency at which the code/module works ( i know that the clock frequency will be decided, but let say i have no info on clock frequency)?

Thanks and regards
bdu

 

[gck]

To answer your question, first important thing we have to know is what's your target device. Is it a FPGA or ASIC?
Ans to Q1 :- If its FPGA then in data sheet you will get the FF delay before hand. If its ASIC then foundry will share this data with you.
Ans to Q2 :- It all depend upon you design. You have to have a understanding of you design. NOTHING else will help you out for detecting multi-cycle path.
Ans to Q3 :- As I said you will have data from either data sheet or foundry, and you understand you have understanding of design. Now, clock frequency can be estimated.

I hope this will help.

 

[lokesh_boddu]

Hi gck

Thanks for ur answers.

what is the difference between back annotation and gate level simulation?

Regards
bdu

 

[gck]

Hi lokesh_boddu,

here is some link which explains your query,
Back Annotation

&

Gate level simulation - Introduction

Hope this helps

 

[bdu_vlsi]

fix setup and hold violation

Hi friends

i am working on virtex 2vpro,

i have setup violation in my design , how to fix setup and hold violation, like how to add buf in path.

please give me tips used to fix the violation

Regards
bdu_vlsi

 

[gck]

Hi, bdu_vlsi,
What kind of design are you working on?
You need to modify you design to avoid setup violation.

Hope this help you

GCK