UART 20Mbps.. PCI... FPGA... Possible?

[Sink0]

Hi,

I need some help. I need to interface a PC/104 Plus with many sensors. I am going to use RS485 for this task but the onboard UART of the PC/104 is too slow. Is it possible to create a UART port with something like 20Mbps baud rate or 2 10Mbps baud rate ports to comunicate via PCI with PC/104 wih an FPGA? If yes any advice?
Would CPLD be a better choice? What is the minimun requirements the CPLD/FPG would need to acomplish this task?

Thank you

 

[FvM]

The UART receiver needs an oversampling clock with e.g. factor 8 of the baud rate. This is more easy to achieve with a FPGA,
that has frequency multiplying PLLs. But a CPLD with a suitable clock cna do it as well.

 

[Sink0]

Is that possible to implement it EP1C3 with 144 pins running at 250Mhz? If not wht would be the minimun requirements to run this "PCI to UART" converter and run the uart at 10 or 20 Mbps baud rate? Can i accomplish this task with just the FPGA or will i need any other device? Should i use A PCI controler as PCI 9030 from PLX or FPGA can handle it alone?

Thank you!

 

[FvM]

EP1C3 would be OK. But you should not run the complete design at 250 MHz (or better an integer multiply of 20 MHz), only the
UART receiver. You need at least a serial configuration device (and a 1.5V core voltage regulator) to operate the FPGA.

MAX II would be another option, it has non-volatile configuration storage, but it no PLL, so it would need a fast clock oscillator.
You can reduce the input clock requirement to 4x Fbaud by operating the UART receiver front end on both clock edges, but it makes
the design more complex and probably isn't recommended, when you are new to this stuff.

 

[Sink0]

I am going to prototype this PCI/104 card with an breakout board. It comes with a EP1C3T144C8, 1.5V and 3.3V voltage regulatiors and a 50Mhz Oscilator. What frequency do you sugest to run sistem? Should i change the oscilator? I could get a EP3C10 but it costs 30USD more and it comes with EPCS4. As i am not going to use this board in my final design i dont think it will be necessary as i can place the configuration device at my peripherycal board. Should i be ok if i place the FPGA with something like 4cm from my PCI bus?

Thank you!

 

[FvM]

EP1C3 with 50 MHz clock should be O.K. You can generate e.g. 160 MHz with the FPGA internal PLL. You additionally need a
configuration device (EPCS1 respectively ST/Numonyx P25M10) for the final design. 4 cm distance sounds good, because
it avoids problems with unterminated traces.

 

[buenos]

hi

try my pci_mini core on www.opencores.org
it is a simple pci target bridge with low resource need and a single verilog file.
https://opencores.org/project,pci_mini
you can also get uarts in source format, so edit the source file to your clocking need.

 

[Sink0]

Woa!! Thats really helps. Now i got a start point. Now i just have to understand your logic replicate that to cyclone. Just one question. I know that it is impossible to predict but is there any equivalency between Xinlix gates and Altera Logic Elements? As you used 14% of the gates i don't know if 2910 LEs would be enough.

PS: I was planning on use the EPCS1 but what is ST/Numonyx P25M10 and wht for am i going to need it?

Thank you for the help!!

 

[buenos]

they should tell something about haw manhy gates equivalent their FPGA is. this is about the same number as it is with xilinx +/-50%.

 

[FvM]

P25M10 is a replacement for EPCS1. For usual logic, you can expect quite similar LE counts for Xilinx and Altera, I think.
But the most simple way is to enter the design and compile it for test.

 

[Sink0]

Thank you for all the help! As soon as i get any result i will post here. Just one question. Is Nios II a Hardware MCU or a SoftMCU that can be implemented on altera FPGA. When you buy a Altera FPGA you have to chose if it comes with NIOS II?

Thank you!

 

[FvM]

Nios II is pure software, the same as Xilinx MicroBlaze.