True Dual Port RAM in Xilinx Spartan-3 FPGA

[mendozaulises]

xilinx dual port ram

Hi all,
I am trying to implement a true dual port (two simultaneous read and Write operations) Block RAM in a Spartan-3 FPGA. According to the xapp463 this can be done. However I don't have the Xilinx Core generator, only ISE 6.1 (project Navigator). When I try to synthesize my VHDL description I got the next warning:

You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time

When trying a different approach i got another warning that said that I had to try instantiating the RAM, I found a template in the Project Navigator, however, I can't compile it in Active-HDL.

Do any of you have an example of this kind of RAM (Instantiate) and how I can synthesize it?

Thanks in Advance,
Ulises

 

[it_boy]

xilinx true dual port ram

if you are instantiating dual port block ram as given by pronject navigator, you need to compile the xilinx library for simulation.
You can find the libraty in
for verilog...
$xilinx\verilog\src\unisims

for vhdl...
$xilinx\vhdl\src\unisims

 

[mendozaulises]

true dual port ram

Thanks, I have already managed to configure the dual port RAM.

 

[hussain.elsaid]

spartan 3 dual port ram

hello, can you tell me how could you manage the dual port ram, as I get the same warning as the first one you have got.

thanks in advance,
Hussain

 

[omara007]

Re: true dual port ram

Thanks, I have already managed to configure the dual port RAM.

Would u please share ur experience being able to do so without the CoreGen ?