Tristate Buffer 15 to 0

[CuST0M1z3]

Is there a way to buffer input(15 downto 0) to get output std_logic only ?

 

[FvM]

You should try to phrase a clear question.

 

[CuST0M1z3]

You should try to phrase a clear question.

At the entrance of the buffer enters signal with width std_logic_vector(15 downto 0).On the output, i wanna get signal with width - std_logic only.

 

[FvM]

Each input bit has to be copied to an individual logic signal.

o15 <= i(15);
o14 <= i(14);
...
o0 <= i(0);

 

[CuST0M1z3]

Each input bit has to be copied to an individual logic signal.

o15 <= i(15);
o14 <= i(14);
...
o0 <= i(0);

i know this, you dont understand my question. I have only 1 output with width of std_logic.Can I somehow merge inputs into this 1 output?

 

[FvM]

i know this, you dont understand my question. I have only 1 output with width of std_logic.Can I somehow merge inputs into this 1 output?

You're the champion of unclear questions! Without specifying a logic operation, the signals can't be merged.

 

[CuST0M1z3]

You're the champion of unclear questions! Without specifying a logic operation, the signals can't be merged.

I am sorry, but my English is not perfect :roll:
I want to realize this logic:
entity Three_st is
port( T: in std_logic;
I: in std_logic_vector(15 downto 0);
O: out std_logic);
end Three_st;

architecture Behav5 of Three_st is

begin
process(I,T)
begin
if (T = '0') then
O <= I;
else
O <= 'Z';
end if;
end process;


end Behav5;

I tried 5 different ways to merge all input signals to only one output, but no one was succesful :-? Please, give to me some guidance.
I know how to increase width of bus,i know how to reduce it to (0 downto 0) but i don`t know how to do the opposite when i need std_logic width only..

 

[FvM]

This operation is undefined O <= I; as long as you can't give a rule for reduction of the 16 bit vector to 1 bit.

E.g. I may be "0001001001110011", what do you want as result for O, '0' or '1' ?

 

[CuST0M1z3]

This operation is undefined O <= I; as long as you can't give a rule for reduction of the 16 bit vector to 1 bit.

E.g. I may be "0001001001110011", what do you want as result for O, '0' or '1' ?

I try this logic too, but i am not sure that it is the right one:

entity Three_st is
port( T: in std_logic;
I: in std_logic_vector(15 downto 0);
O: out std_logic);
end Three_st;

architecture Behav5 of Three_st is

begin
process(I,T)
begin
if (T = '1') then
if (I = "0000010000000000") then
O <= '1';
else
O <= '0';
end if;
else
O <= 'Z';
end if;
end process;


end Behav5;

 

[FvM]

I try this logic too, but i am not sure that it is the right one

There are actually 65536 possible bit combinations for the input vector. If your not sure about your intention in reducing it, how should know?