Timing Delay in FPGA

[dzafar]

Hello there,

What is the difference between Logic Delay and Routing Delay?

Also is logic delay the same as Gate Delay?


Thanks in advance

 

[barry]

Logic delay is the delay through the logic (gates, registers, etc.). Routing delay is the delay through the routing (conductors).

 

[dzafar]

Thanks for your reply Barry

I do have a followup question though! In the figure below, when they say "...routing delays and gate delays are lumped together..." they are combining the gate delay with the delay of the wire. Does that mean routing delay does not necessarily have to have a capacitor?



Thanks again

 

[barry]

Not sure what you mean about 'having a capacitor'. Routing delay is a function of physics-the materials used in the FPGA as well as the length of the physical routes. Capacitance is a fact of life, but there's no actual 'capacitor' in there.

 

[shaiko]

but there's no actual 'capacitor' in there

Well, any transistor gate is a capacitor in essence...so there's some rational behind the OP's question.

But dzafar,
I think you're approaching it the wrong way...when analysing logic delays inside an FPGA - you stay within the scope of LUTs/ Fanouts /Distances between registers/ etc.
You don't deal with actual circuit capacitance as you would in simple discrete circuit.

 

[ads-ee]

You don't deal with actual circuit capacitance as you would in simple discrete circuit.

Besides this an FPGA's STA tools accounts for this based on the number of loads and the routing used. It is all part of the vendors timing files. This is unlike an ASIC where the delays have to be calculated based on your routing, the FPGA routing is already fixed so the vendor can model all the timing including any parasitic capacitance.