Timing analyses using Xilinx Timing analyzer

[Mkanimozhi]

Timing analyses

Hi Experts,
Using Xilinx Timing analyzer shall we do the timing analysis of the combinational design.if it is possible how can we do.

Regards,
Kanimozhi.M

 

[Aser]

Re: Timing analyses

When I want to do the timing analysis of the combinational network in FPGA,
I usually attach the registers to its inputs, outputs.
Then I synthesize, P&R it as usual but with the severe CLOCK constraints,
and see the timing reports.
Xilinx shows a set of critical routes with all the delays, which doesn't satisfy the constraints.

 

[dkk1980]

Re: Timing analyses

You can apply a PAD to PAD constraint in ISE and see whether it meets.

dkk

 

[sanjayk]

Timing analyses

open Timing analyzer. Open the Timing->Run_analysis and then provide the paths.