time measurement in simulation

[omidsht]

Hello , How can I measure how much time does it take to execute a whole
process or a part of a process in real-time(in fpga) ? is there any tool in modelsim or questasim or activehdl for this purpose ?
thanks in advanced.

 

[palai_santosh]

Most of the simulators will show you.
by the way what you want to measure exactly??

 

[omidsht]

I want to see how much time it takes to do a part of my process code or a whole process code in vhdl

 

[FvM]

There's nothing to measure. All processes in a FPGA design are executed in parallel without any idle time. So the simulation time is identical to the process time requirement.

If different question would be, if the clock frequency of particular design entity or the design as a whole can be increased without creating timing violations. It can be answered by the timing analysis tool, not the simulator.

 

[omidsht]

I know that processes are in parallel .
what i mean is this :
imagine we have only one process, which there ar some sequential instructions and we have a function too.
I want to know how much time does it take to execute this process from beginning to end , and also how much time does it take to execute the function in the process if it is triggered.

another question : what does timing analysis tools , what they do ? can you give their names ?

thanks for contribution

 

[FvM]

how much time does it take to execute this process from beginning to end

Either one or zero clock cycles, depending on the process.

Most synthesis tools have built-in timing analysis. Depends on your FPGA vendor.

 

[Aser]

There is in VHDL the standard function NOW which returns the current simulation moment.
The time measurement looks like:
T1:=NOW;
--simulation runs
T2:=NOW;
T:=T2-T1;