synthesis of unused logic in RTL

[oAwad]

Hello all,

I have a question regarding RTL synthesis, if I define KEY_SIZE in my top level entity like this (note the value assigned is zero)

   generic        (
                  KEY_SIZE             :  in    integer range 0 to 2 := 0
                  );

and if my RTL design has if conditionals checking if (KEY_SIZE equals to 1 or 2) and will do other operations accordingly.

So I want to know how will the synthesis tool translate this to gate level. Will it consider the conditions when (KEY_SIZE equals 1 or 2) and the logic done accordingly ?

I think the tool should be able to optimize this situation and remove all logic related to (KEY_SIZE equals 1 or 2) as KEY_SIZE is not an input...it's hard-coded....but I like to hear from experts in these tools.

Thanks

EDIT: I'm using synopsys Design Compiler

 

[FvM]

The logic will be generated according to the actual value of the generic KEY_SIZE, other code won't be synthesized but still checked for correct syntax.