Speed in PCI and limitation of it

[nguyenvanthien]

Hi all,
I'm studying the PCI. If clock is 33 MHz, why transfer rate is 133 MBps? And what is limitation of speed in PCI?
Thank you very much!

 

[BradtheRad]

MBps means megabits per second (normal terminology when talking about transfer rates). Perhaps 133 MBps is executed by a different IC (for I/O purposes) from the one that executes 33 MHz (for main card functions)?

The manufacturer probably could make the entire card operate at 133 MHz, but it would require upgrading all IC's to a faster speed capability, with resulting higher expense, etc. So they leave it at the slower speed because that is adequate for most card functions.

 

[srizbf]

clock is 33MHZ.
For each clock pulse , 4 bytes are transferred in
basic default mode of PCI Bus.
So , it is 133MBytes /sec (~=4x33)

Limitation of speed is based on the PCI cards connected to the Bus.

 

[nguyenvanthien]

I don't understand clearly: 33Mhz ~ 30.3 ns (period). And, in 1 clock pulse, 32 bit are transferred so period of 1 bit will 1 ns or less???
Can you draw timing to explain for me?
Thank you very much.

 

[Dan Mills]

PCI (As opposed to PCI-E) is a 32 bit parallel bus so it can move 32 bits of data at a time.
The downside is that laying such things out to run at real speed is a nightmare (Lots of careful length matching, and problems with stubs on the cards), hence the move to the much easier to lay out (In spite of its far greater clock speed) serial design with PCI-E which is point to point and does clever link training to remove much to the timing pain.

About the only place you see very high speed parallel buses these days is in memory interfaces, and there is a reason people are scared of doing DDR3 layouts.

Regards, Dan.

 

[srizbf]

it is not 1 bit in 1 ns.
it is entire 32 bits when clock is active.
it is a parallel transfer.

 

[hobbyckts]

Actually it is 33.33MHz, So calculation is as follows

33.33 MHz × 32 bits ÷ 8 bits/byte = 133 MB/s