Simulating verilog netlists

[hacksgen]

Hi,

Can anyone tell me how can one simulate a verilog netlist in cadence virtuoso editor. I have a verilog module which has been synthesized into a verilog gate level netlist using synopsys. I want to simulate this gate level netlist in cadence without importing this synthesized file as schematic in cadence. Can anyone tell how to do this.

I have tried to simulate this by creating a functional view of this gate level netlist and create a symbol and use tht in the schematic for simulation purposes. However it does not work for me.

Any ideas as to what i should do?

Thanks

 

[cafukarfoo]

Hi Hackgen,


I think you must missing the power connection for your logic gate.

For example,
you can view the logic gate from your library. It might have a VDD and GND pin.

Make sure you connect those VDD and GND pin correctly.

If not, your output will be always '0' because the gate is not power up.

Hope this help.

 

[hacksgen]

Hi,

I connected the powersupplies. The schematic level simulation works fine but it is too slow. I want to do gate level verification of the synthesiszed netlist in cadence.

Thanks