Simple concurrent statement written for fpga, value doesn't change.

[Ruddwijk]

So, i have a fairly simple code written with concurrent statements. However, when testing, LdBuf gives "0000000000000001" and then doesn't change with D_Add. Have i missed something? Not experienced in writing concurrent code, or using others.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;


entity DestinationDecoder is
    Port ( W: in  STD_LOGIC;
           D_Add: in  STD_LOGIC_VECTOR (3 downto 0);
           Ld: out  STD_LOGIC_VECTOR (15 downto 0));
end DestinationDecoder;

architecture Behavioral of DestinationDecoder is
signal LdBuf: std_logic_vector(15 downto 0):= (others => '0');
begin

LdBuf <= (to_integer(unsigned(D_Add(3 downto 0))) => '1', others => '0');
Ld <= "0000000000000000" when (W = '0') else
	LdBuf;

end Behavioral;

 

[TrickyDicky]

Sorry - misread code originally.

Check that the RTL diagram actually has the hardware you think. I know quartus has had bugs in the past with this type of code.

- - - Updated - - -

try this code instead, it is functionally identical:

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Code VHDL - [expand]
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process(D_Add)
begin
  LdBuf <= (others => '0');
 
  for i in LdBuf'range loop
    if unsigned(D_Add) = i then 
      LdBuf(i) <= '1'
    end if;
  end loop;
end process;

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