signed multiplication data size ISE warnings

[dareon]

I have been working on converting my code from using integer math to signed math.

I am using
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

in my code I am multiplying to signed 16 bit numbers.
signal SINE_IN : std_logic_vector(15 downto 0); --From ADC
signal SINE_TABLE : signed(15 downto 0); -- From Table

-- These numbers are multiplied and stored in a array (32 position shift register)

Mult_ARRAY(0) <= signed(SINE_IN) * SINE_TABLE;

The problem is the compiler gives me warnings depending on the width of the array.

If I make the array 32 bits wide (31 downto 0) I get 32 warnings (32 position array)

WARNING:Xst:2677 - Node <Mult_ARRAY_8_31> of sequential type is unconnected in block <Position>.

If I make the array 31 bits wide (30 downto 0) I get

WARNING:Xst:643 - "C:/VHDLPrograming/Nano/DNPREV01/position.vhd" line 183: The result of a 16x16-bit multiplication is partially used. Only the 31 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.

I feel like 31 bits should really have enough space since in theory it is really 2^15 *2^15 squared and a sign bit. I want to make sure I'm not somehow losing the sign bit or something important.... I'm am just working on doing the coding now I won't have the hardware for about a week to really test it.

I am really new to VHDL coding and am using ISE 11.5

Thank You

Russell

---------- Post added at 09:50 ---------- Previous post was at 09:46 ----------

Also in the 31 bit scenario I get another warning

WARNING:Xst:1610 - "C:/VHDLPrograming/Nano/DNPREV01/position.vhd" line 183: Width mismatch. <Mult_ARRAY<0>> has a width of 31 bits but assigned expression is 32-bit wide.

 

[alexan_e]

WARNING:Xst:1610 - "C:/VHDLPrograming/Nano/DNPREV01/position.vhd" line 183: Width mismatch. <Mult_ARRAY<0>> has a width of 31 bits but assigned expression is 32-bit wide.

The result of your multiplication is 32 bit so when you try to fit this in 31 bit you get this warning

I think there is a problem with your Mult_ARRAY, are you sure that you declare a 32 x 32bit array and not 32 x 1bit?

Also try to store the result to a signal 32 bit wide to see if it works.

Alex

 

[FvM]

Generally, the result of signed 16x16 multiply is 32 bit wide. But the result is not using the full range of the 32-bit signed number. This has nothing to with HDL, but is the general behaviour of 2's complement number representation. You can shift the result right by one bit (or cut the MSB), but you need a special handling of the value 0x8000*0x8000, that would cause an overflow in this case.

I don't however understand the "unconnected" warning.

 

[dareon]

This is my declaration

type signed_array32 is array(31 downto 0) of signed(31 downto 0);
signal Mult_ARRAY : signed_array32;

 

[alexan_e]

I tried the following and works fine for me, you can post your code if you want so i try it in ise 11.4

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

entity test is
  port ( input : in std_logic_vector(15 downto 0);
			output : out std_logic_vector(31 downto 0)
		);
		  
end test;

architecture Structural of test is
  signal SINE_IN : std_logic_vector(15 downto 0); --From ADC
  signal SINE_TABLE : signed(15 downto 0):="1010101010101010"; -- From Table
  type signed_array32 is array(31 downto 0) of signed(31 downto 0);
  signal Mult_ARRAY : signed_array32;

begin
 
SINE_IN <=  input;
Mult_ARRAY(0) <= signed(SINE_IN) * SINE_TABLE;
output<=	STD_LOGIC_VECTOR(Mult_ARRAY(0));

end Structural;

 

[dareon]

My

WARNING:Xst:643 - "C:/VHDLPrograming/Nano/DNPREV01/position.vhd" line 183: The result of a 16x16-bit multiplication is partially used. Only the 31 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.

warning seems to have gone away even though I am doing the 16x16 into a 31 bit number. I changed some other stuff but nothing that should have affected that.

Thank You for the quick replies guys.

Russell