Shared resource access

[Artlav]

Hello.

I'm trying to figure out how to orchestrate an asynchronous shared access of two independent blocks to a single resource, and describe it in Verilog.

Case in question:

//----------------------------------------------------------------------------//
`include "arbiter.v"
//----------------------------------------------------------------------------//
module testchip(reset,clock,x);
input  reset,clock;
output [31:0] x;
//----------------------------------------------------------------------------//
reg req_0,req_1,skip_0,skip_1;
wire grant_0,grant_1;
wire clk_2;
//----------------------------------------------------------------------------//
always @(posedge clock)clk_2<=!clk_2; 
//----------------------------------------------------------------------------//
//Arbiter, see http://www.asic-world.com/examples/verilog/arbiter.html
arbiter xa(.clk(clock),.rst(reset),.req0(req_0),.req1(req_1),.gnt0(grant_0),.gnt1(grant_1));
//----------------------------------------------------------------------------//
//Actions
always @(posedge grant_0 or posedge grant_1)
begin
 if(grant_0)begin
  //Do first
  x=x+1;
  req_0=0;
  skip_0=1;
 end else begin
  //Do second
  x=0;
  req_1=0;
  skip_1=1;
 end
end
//----------------------------------------------------------------------------//
//Request first
always @(posedge clock)
begin
 if(skip_0)skip_0=0;else req_0=1;
end
//----------------------------------------------------------------------------//
//Request second
always @(posedge clk_2)
begin
 if(skip_1)skip_1=0;else req_1=1;
end
//----------------------------------------------------------------------------//
//Init
initial
begin
 skip_0=0;
 skip_1=0;
 req_0=0;
 req_1=0;
end
//----------------------------------------------------------------------------//
endmodule
//----------------------------------------------------------------------------//

Each of the blocks set the request variable, indicating to arbiter that it wants to get access, once the grant is signalled it does the access and clears the request.

The problem is that i'm getting "Can't resolve multiple constant drivers for net" errors while trying to synthesise it.

Apparently, only one always block can set a reg/signal.

Thus, the question is - how can i organize this without multiple blocks setting some shared register?
How to implement a simple mutex/semaphore?

More generally, how to implement the shared access like that properly?