Random Variable help.

[nsherwoo]

Hey all,

Trying to get a random number between 0 and 15.

I'm trying to use Uniform and I'm getting this error:
"VHDL Unsupported Feature error at <location>: cannot synthesize non-constant real objects or values"

hitcheck: process(address, hit, hit_index)
variable tag_bits: std_logic_vector(5 downto 0);
variable seed1, seed2: positive:=42;
variable rand: real; <-----it's complaining about this variable.
variable int_rand: integer;
begin
UNIFORM(seed1, seed2, rand);
tag_bits := address(7 downto 2);
if tag_bits = tag_array(0) then
hit <= '1';
hit_index <= 0;
.....--lots of stuff
else
hit<= '0';
int_rand := INTEGER(TRUNC(rand*15.0));
hit_index <= int_rand;
end if;

end process;

Any help would be much appreciated.
I found a similar snippet of code here:
https://www.velocityreviews.com/forums/t22430-random-number-generator.html
(last reply is someone who like me is getting this error.

edit-
Sorry, I should mention I have these two lines much higher in my code.
use ieee.math_real.all; -- for UNIFORM, TRUNC
use ieee.numeric_std.all; -- for TO_UNSIGNED --Don't think I'm using this one.

 

[bigdogguru]

The error message:

"VHDL Unsupported Feature error at <location>: cannot synthesize non-constant real objects or values"

points out what exactly the problem is with the code.

Objects of type Real - floating point numbers cannot be mapped to hardware and therefore are not supported.

**broken link removed**

Reals and Floats can be used at compile time to generate LUTs and other constants. However, to make use of floating point numbers at design synthesis, you would have to incorporate a floating point unit core into your design. An example:

OpenCores double floating point core

A pseudo random sequence generator (PRSG) which may serve your purpose:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity random is
    generic ( width : integer :=  32 ); 
port (
      clk : in std_logic;
      random_num : out std_logic_vector (width-1 downto 0)   --output vector            
        );
end random;

architecture Behavioral of random is
begin
process(clk)
variable rand_temp : std_logic_vector(width-1 downto 0):=(width-1 => '1',others => '0');
variable temp : std_logic := '0';
begin
if(rising_edge(clk)) then
temp := rand_temp(width-1) xor rand_temp(width-2);
rand_temp(width-1 downto 1) := rand_temp(width-2 downto 0);
rand_temp(0) := temp;
end if;
random_num <= rand_temp;
end process;

testbench produces random integer 0 to 15:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY testbench IS
END testbench;

ARCHITECTURE behavior OF testbench IS 
   --Input and Output definitions.
   signal clk : std_logic := '0';
   signal random_num : std_logic_vector(3 downto 0);
   -- Clock period definitions
   constant clk_period : time := 1 ns;
BEGIN
        -- Instantiate the Unit Under Test (UUT)
   uut: entity work.random generic map (width => 4) PORT MAP (
          clk => clk,
          random_num => random_num
        );
   -- Clock process definitions
   clk_process :process
   begin
                clk <= '0';
                wait for clk_period/2;
                clk <= '1';
                wait for clk_period/2;
   end process;

END;

This PRNG is from VHDLGuru's Blog:

**broken link removed**

Hope this clears things up a little.

 

[nsherwoo]

Thanks for the reply.

I think what I ended up doing was very similar.

I took code found here:
https://rvk.tripod.com/index-10.html
and converted it to 4 bits to get my 0 to 15 integer range.

Thanks again.