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Question about OC PCI Cores

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Hi, i am trying to use OpenCores PCI Bridge but i have some doubts.

Whats exactly is the Image Address and how it works?

When i am receiving some information on PCI Target, how can i define the
WishBone Slave that is being addressed?

When i am sending some information with a WishBone Master to the Bridge
Slave, how can i define to which PCI on the BUS i am addressing?

Thank you!
 

Yep, they do, but i am having some problemes to understand it becouse i think they assume you already have some experience with PCI (or i am looking at the wrong port of the documentation). I will run some tests tomorrow and see what happens hehe bu any help would be apreciated
 

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