mahesh690
Newbie level 3
Hi,
I am designing a Transmitter using verilog,I want to synthesize the design to FPGA and then get the modulated bits through the MGT(Multi Gigabit Transmitter),my problem is since modulation formats like QPSK have negative constellation points they take more bits than positive constellation points.Any idea how to get around this.
Thanks,
Mahesh
I am designing a Transmitter using verilog,I want to synthesize the design to FPGA and then get the modulated bits through the MGT(Multi Gigabit Transmitter),my problem is since modulation formats like QPSK have negative constellation points they take more bits than positive constellation points.Any idea how to get around this.
Thanks,
Mahesh
