Priority keyword of System Verilog

[fragnen]

Do the priority keyword of System Verilog make an incomplete case statement behave as a full case?

 

[dave_59]

The priority and unique keywords before a SystemVerilog case statement do not change the execution behavior of the case statement. However, they do provide violation errors if the statement is coded in such a way that no branch is taken. This helps ensure what gets simulated matches the functionality of what is synthesized.

 

[fragnen]

The priority and unique keywords before a SystemVerilog case statement do not change the execution behavior of the case statement. However, they do provide violation errors if the statement is coded in such a way that no branch is taken. This helps ensure what gets simulated matches the functionality of what is synthesized.

Does it mean we should use both priority and full_case pragma together for a case statement where the case statement is incomplete I.e. a few branches are not taken?

 

[dave_59]

http://www.sunburst-design.com/papers/CummingsSNUG2005Israel_SystemVerilog_UniquePriority.pdf

 

[fragnen]

http://www.sunburst-design.com/papers/CummingsSNUG2005Israel_SystemVerilog_UniquePriority.pdf

According to this paper priority behaves like a full_case. That means priority makes a case statement whose all case items are not defined to behave like a full case. Is not it?