Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[SOLVED] Plot in LTSpice - Vt0 vs. Vgs

Status
Not open for further replies.

surpriya.7

Newbie level 4
Joined
Jul 1, 2008
Messages
7
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,283
Activity points
1,325
Hello,

Im trying to plot Vt0 vs. Vgs keeping a Vds constant.
In the 'pick a visible trace' list, I can see all the currents and the circuit voltages - but not the device parameters.

Please find the circuit below - its a real simple circuit.
Any help is appreciated.

Thanks
ssti

20_1285458603.png
20_1285458603.png
 
Last edited by a moderator:

Vt0 is a constant of the model so there is no sensible plot with that as the x axis.

Keith
 

Are you people speaking of some kind of parametric anayisis?
 

In some SPICEs you can pick off model params - look for .mp()
or something like that.

The use for such sims is in things like predicting a Vgs-derived
pin electrical parameter, against WAT limits (presuming model
parameter ranges are fitted against WAT data). Though other
things (deltaL, k', Nss) will also play.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top