xihuwang
Member level 2
PLL has big phase offset
Hi:
An on chip PLL design has big phase offset which is about 2ns between
clk in and clk feedback of PFD.
The parameter is below :
fclkin=4-20MHz Icp = 2.5uA - 20uA , Kvco = 100MHz - 300MHz, N=16
If follow the below design discriptoin:
Funit = 1/20 Fclkin
C1 = 1/20 C2
ξ = 1
The R and C will too large for on-chip clock sysnthesis. So I want to
know What is your descision on the R and C 's value .( I hope C smaller
than 100pF, R smaller than 15k, and voltage variation of LPF is below 1mV)
Hi:
An on chip PLL design has big phase offset which is about 2ns between
clk in and clk feedback of PFD.
The parameter is below :
fclkin=4-20MHz Icp = 2.5uA - 20uA , Kvco = 100MHz - 300MHz, N=16
If follow the below design discriptoin:
Funit = 1/20 Fclkin
C1 = 1/20 C2
ξ = 1
The R and C will too large for on-chip clock sysnthesis. So I want to
know What is your descision on the R and C 's value .( I hope C smaller
than 100pF, R smaller than 15k, and voltage variation of LPF is below 1mV)