PLL for GSM application divder Help

[Er_SJSU]

The question is regarding my MS Project.
I am designing PLL for GSM application using 45nm technology
output frequey range is 890-915Mhz with 200khz channel spacing, so we will have 124 channels spaced at 200khz apart.
The problem is for divider Nmin=890Mhz/200khz=4450 and Nmax=915Mhz/200khz=4575.
How to get this big divider numners? and how to vary them i.e channel select?
Any releted paper or idea will help.
Thanks

 

[sanbanjji]

use dual modulus counter

 

[tony_lth]

Why not ref Analog devices synthesizer datasheet? In true, I don't understand your question.

 

[sanbanjji]

If you want a divider to divider down the freq from 4450 to 4575, You need build a dual modulus section, such as div4/div5, and a 13-bit counter.