Phase Shift Full Bridge converter has been superceded? ..(by ZVS Full Bridge)

[zenerbjt]

Hi,
Just noticed the ISL6752 ZVS Full Bridge Controller promises to be everything that the PSFB is, but simpler (and therefore better). Page 1 says...

ISL6752

https://www.renesas.com/eu/zh/document/dst/isl6752-datasheet

The PSFB is known to present a minefield of potential failure mechanisms for the unwary (eg during transients and startup) . And as the following thread shows, (latterly) the PSFB circuit common to most App Notes requires quite some "augmentation" to make it optimal...

Phase Shift Full Bridge SMPS is massively over-hyped?

Hello, The Phase Shift Full Bridge (PSFB) converter is a hoax. –The LTspice simulation attached of a “plain” Full Bridge SMPS bears this out. PSFB claims to be able to reduce switching losses compared to the “plain” Full Bridge SMPS. However the PSFB does have Turn-OFF switching losses, just...

www.edaboard.com

Have we seen the end of the PSFB?

 

[Easy peasy]

the ISL6752 ZVS Full Bridge Controller - is a new chip - and therefore likely has a few bugs - they way they do the CT and the slope comp - points to engineers who haven;t really got to grips with the PhSFB

by the way all PhSFB's are ZVS at full load down to some light load ( typ 20 - 40 % ) - how far down depends on the hardware design - there are lots of papers on how to extend the lossless switching range.

Standard toplogy is hard switched from 0 - 30% load approx ...

 

[zenerbjt]

the way they do the CT and the slope comp - points to engineers who haven;t really got to grips with the PhSFB

Yes, on page 4 and page 5 of the ISL6752 datasheet they have the current sense transformer referenced to the Vdd rail, which appears to be totally wrong. On pages 12 and 13 they show a correct schematic for the current sense transformer though.

--- Updated Jan 3, 2021 ---

Actually, would you agree that the drive waveforms for the lower bridge fets and the synchronous fets on page 15 and 16 of the ISL6752 datasheet are mostly totally incorrect?....

Fig 19 is actually correct, but its on a “knife edge”, there being no delay between switching of the lower bridge fets and synch fets. But its “basically” correct, since each synch fet is on for its relevant bridge fet’s on-time, and also for the “freewheel” time.

Fig 20 and Fig 21 show each synchronous fet being ON when either left or right side lower bridge fets are on, and this is incorrect.

 

[Easy peasy]

you can have the CT in the +ve rail - but this places a limit on the phase shift as the CT needs time to reset - typically 95% overlapping abs max with possibly 150 V reset volts on the CT sec ( LV side ) the diode needs to be a good one - low capacitance

it is a good idea ot have some small bus cap on the RHS of the CT so that there is some where for the current to go during switch off of the mosfets ...

Sec side synch rect is a lil bit tricky for current doubler as the fets need to be on in the "dead time" of the phase shift - AS LONG AS the current in the current double chokes is continuous...! when you get to discontinuous / light load - the drive to the synch rect fets is more complex ...

 

[zenerbjt]

you can have the CT in the +ve rail

Thanks, I agree, in certain situations, though I believe the CT schems on pages 4 and 5 of the ISL6752 datasheet won’t work.
The attached simulation shows this, it is a similar situation and CT but just with a different control chip. The Current sense pin of ISL6752 is expecting a voltage ramp between 0 and 1V.....the CT has been "referenced" to 12V, so will be giving a voltage well above 1V to the current sense pin of ISL6752.

Sec side synch rect is a lil bit tricky for current doubler as the fets need to be on in the "dead time" of the phase shift - AS LONG AS the current in the current double chokes is continuous...! when you get to discontinuous / light load - the drive to the synch rect fets is more complex ...

Thanks, I agree with all this, though this isn’t relevant to the Fig20 and Fig21 (pages 15 and 16) of the ISL6752 datasheet which show incorrect drive waveforms for the synch rects.