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I think it depends. It is my understanding that a DCO(Digitally Controlled Oscillator) can simply be a VCO that is controlled digitally (e.g., with a DAC), or, it can actually be an NCO. If your DCO has an analog output, then obviously you can't just drop in an NCO.
I think it depends. It is my understanding that a DCO(Digitally Controlled Oscillator) can simply be a VCO that is controlled digitally (e.g., with a DAC), or, it can actually be an NCO. If your DCO has an analog output, then obviously you can't just drop in an NCO.
I am planning to replace a dco that is dac + vco and output is square pulse. If i replace it with an NCO without a look up table(i.e, accumulator dco) will it be okay?
I am planning to replace a dco that is dac + vco and output is square pulse. If i replace it with an NCO without a look up table(i.e, accumulator dco) will it be okay?
A DAC+VCO will be more stable and accurate than a accumulator DCO (unless you've found a way to run the FPGA NCO at 10 GHz, i.e. to get 100ps of output clock edge jitter). If your application doesn't require a low jitter clock then an NCO will work just fine, but as part of an ADPLL?...I'm not so sure about that.
A DAC+VCO will be more stable and accurate than a accumulator DCO (unless you've found a way to run the FPGA NCO at 10 GHz, i.e. to get 100ps of output clock edge jitter). If your application doesn't require a low jitter clock then an NCO will work just fine, but as part of an ADPLL?...I'm not so sure about that.
Sure you can simulate an NCO I've used them for packet processing designs where the aggregate egress rate had to be very precise, but the inter-packet jitter was a don't care.
Just don't expect a jitter free clock from an NCO unless you use a simulated 10 GHz or greater clock to run the NCO. Of course that means it is just a simulation NCO, which you can't implement in any FPGA in 2015 (maybe in 2025 on a Xilinx 2 nm Gigatex part ;-)).
Sure you can simulate an NCO I've used them for packet processing designs where the aggregate egress rate had to be very precise, but the inter-packet jitter was a don't care.
Just don't expect a jitter free clock from an NCO unless you use a simulated 10 GHz or greater clock to run the NCO. Of course that means it is just a simulation NCO, which you can't implement in any FPGA in 2015 (maybe in 2025 on a Xilinx 2 nm Gigatex part ;-)).
You read my post? That's what I said...use a clock of at least 10 GHz to run the "simulated" NCO to get about 100 ps of clock jitter, if you need better performance then use a higher frequency clock to drive the NCO.
Consider the technique used in Analog Devices' AD9851 and others. Se the data sheet for examples.
DDS running at 150MHz plus sine LUT plus DAC. Feed that to a 7th order analogue 70MHz low pass filter to get an analogue sine wave. Feed that sine wave to a comparator to get a square wave. The LPF removes the harmonics and greatly reduces the jitter below 6.6ns/150MHz.
Consider the technique used in Analog Devices' AD9851 and others. Se the data sheet for examples.
DDS running at 150MHz plus sine LUT plus DAC. Feed that to a 7th order analogue 70MHz low pass filter to get an analogue sine wave. Feed that sine wave to a comparator to get a square wave. The LPF removes the harmonics and greatly reduces the jitter below 6.6ns/150MHz.
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