NMOS vs PMOS leakage current

[vnramkrishnan]

why PMOS leakage current(Ioff) is more than NMOS. Plz specify reason other than mobility ratio.

 

[dick_freebird]

You should look at the drain-gate curves and see for yourself.

Often PMOS has a higher subthreshold slope and for the same
target VT, you will need more positive Vgs to drive subthreshold
conduction to below the leakage floor, than you would negative
voltage on the NMOS.

There can also be issues like poly depletion that make the work
function different (variably) than designed, or even act like an
effectively thicker gate ox. This depends on implant range,
dose, drive & activation.

PMOS is sometimes allowed shorter channel than NMOS because
of different reliability responses. But that can elevate leakage
despite not accruing so much device drift.

If you were looking for specific facts more than conjecture, you
would be asking your foundry directly.

 

[kwkam]

It is depends on the process. Most of todays CMOS process have similar Ioff current for both NMOS & PMOS