Needs explanation... thanks

[mjvm171]

I found this code as a part of a whole other code for a clk counter I think, but I can't understand it much and I really need for a project in school... Please help:| thank you

gen_clken: process(clk, nReset)
begin
if (nReset = '0') then
cnt <= (others => '0');
clk_en <= '1'; --'0';
elsif (clk'event and clk = '1') then
if (cnt = 0) then
clk_en <= '1';
cnt <= clk_cnt; -- loading of clk_cnt when clk_en is disabled
else
if (slave_wait = '0') then
cnt <= cnt -1;
end if;
clk_en <= '0';
end if;
end if;

end process gen_clken;

:grin:

 

[alexan_e]

What part of the code you don't understand

---

Code VHDL - [expand]
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gen_clken: process(clk, nReset)
begin
    if (nReset = '0') then      -- if reset input is 0
        cnt <= (others => '0');
        clk_en <= '1'; --'0';
    elsif (clk'event and clk = '1') then    -- else on rising edge of the clock
        if (cnt = 0) then
            clk_en <= '1';
            cnt <= clk_cnt; -- loading of clk_cnt when clk_en is disabled
        else
            if (slave_wait = '0') then
                cnt <= cnt -1;
            end if;
            clk_en <= '0';
        end if;
    end if;
 
end process gen_clken;

---

Alex