need verilog pll coding for xc9572 cpld device

[Lokesh Waran]

Dears,

i have external clock frequancy of 40 Mhz in xc9572xl CPLD device ,i am very new for Verilog can anyone answer me for phase lock loop for obtain Fcco (output core clock frequency ) 120 MHz .how can i write coding for that?


thank you very much for all visitors and replys

 

[FvM]

Generally speaking, it's not possible without a dedicated PLL block which includes an analog VCO.

There are nevertheless ways to implement a kind of PLL in pure digital logic, I guess it win't fit xc9572

https://www.edaboard.com/threads/194547/

 

[Lokesh Waran]

Generally speaking, it's not possible without a dedicated PLL block which includes an analog VCO.

There are nevertheless ways to implement a kind of PLL in pure digital logic, I guess it win't fit xc9572

https://www.edaboard.com/threads/194547/

thankkkkkkkkkkkkk youuuuuuuuuuu very much for your replay ..............

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hi...! but in xc9572xl device data sheet they have given that we can run the core frequency up to 120 Mhz .
but, external maximum crystal frequency is 40 MHz. So ,how should I achieve 120 MHz core clock?
Is this possible with external crystal or any internal PLL code.
whether this is to be achieved only with PLL?.If yes means How to done with verilog/vhdl code? (design tool: Xilinx ISE 13.4)