Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Need help to implement parallel chien search algorithm

Status
Not open for further replies.

zoomkrupesh

Newbie level 4
Joined
Feb 3, 2009
Messages
6
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,329
Hi,

I want to implement parallel chien search algorithm on FPGA.I found some material in which there are two methods are shown to implement the parallel chien search algorithm.
In one method there are pt different g.f(2) multiplier(a^1,a^2,a^3,a^4....a^pt) are used.
while in other method there are only t multiplier are used where t = no.of error correction bits.This t multiplier used p times where p=no.of parallel data bits.

I want to implement the second one because it takes less time to implement only t multiplier.I am confused that how to initialize the register with lambda(output from the error polynomial block in bch decoder)

So can anyone guide me how to implement it.

One more thing, does any one know how to implement g.f constant multiplier in a easy way.I am designing g.f constant multiplier for g.f(2^13) and I am deriving the equation manually which takes lots of time.

Thanks in advance.

Regards,

Krupesh.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top