[SOLVED] Need help for simulation problem of Xilinx 12.3 ISE Webpack

[moonnightingale]

I am not getting correct waveform. I have attached code and waveform.Kindly look into code and see where is mistake

`timescale 1 ns / 1 ps
module first(c,a,b);
output c;
input a,b;
and (c,a,b);
endmodule

// Test Bench is written
module t_first;
reg t_a,t_b;
wire t_c;
first M1(t_c,t_a,t_b);
initial
begin
#5000 $finish;
end
initial
begin
t_a=0;
t_b=0;
#1000 t_a=1;t_b=1;
#1500 t_a=0;t_b=0;
end
endmodule

 

[mrflibble]

Hi moonnightingale,

The answer is right there in your screenshot.

Your simulation only runs for 1000 ns, which incidentally is the default setting in ISE 12.3 for a simulation run. You can change it in Process => Process Properties => Simulation Run Time.

hope that helps!

 

[moonnightingale]

Thanks a lot for ur help