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NangateOpenCellLibrary_slow_conditional.v 1662 timing violation

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abu9022

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Hi Friends

can you help me, how to solve the following error(Timing Violation) while running VCS simulation
Code: 
Chronologic VCS simulator copyright 1991-2011
Contains Synopsys proprietary information.
Compiler version E-2011.03-SP1; Runtime version E-2011.03-SP1;  Nov 12 18:32 2014
Doing SDF annotation ...... Done
LEON-2 generic testbench (leon2-1.0.30-xst)
Bug reports to Jiri Gaisler, jiri@gaisler.com

Testbench configuration:
32 kbyte 32-bit rom, 0-ws
2x128 kbyte 32-bit ram, 2x64 Mbyte SDRAM


"NangateOpenCellLibrary_slow_conditional.v", 1662: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\sregs_reg[PIL][1]
    $setuphold( posedge CK:32798, posedge D:32798, limits: (0,1) );

"NangateOpenCellLibrary_slow_conditional.v", 1662: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\sregs_reg[PIL][1]
    $setuphold( posedge CK:32798, posedge D:32798, limits: (0,1) );


"NangateOpenCellLibrary_slow_conditional.v", 1662: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\sregs_reg[PIL][1]
    $setuphold( posedge CK:40830, posedge D:40830, limits: (0,1) );


"NangateOpenCellLibrary_slow_conditional.v", 1662: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\sregs_reg[PIL][1]
    $setuphold( posedge CK:43982, posedge D:43982, limits: (0,1) );

0


"NangateOpenCellLibrary_slow_conditional.v", 1662: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\sregs_reg[PIL][1]
    $setuphold( posedge CK:49094, posedge D:49094, limits: (0,1) );


"NangateOpenCellLibrary_slow_conditional.v", 1662: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\sregs_reg[PIL][1]


"NangateOpenCellLibrary_slow_conditional.v", 1662: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\sregs_reg[PIL][1]
    $setuphold( posedge CK:56102, posedge D:56102, limits: (0,1) );


"NangateOpenCellLibrary_slow_conditional.v", 1662: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\sregs_reg[PIL][1]
    $setuphold( posedge CK:58262, posedge D:58262, limits: (0,1) );

1


"NangateOpenCellLibrary_slow_conditional.v", 1662: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\sregs_reg[PIL][1]
    $setuphold( posedge CK:59946, posedge D:59946, limits: (0,1) );


"NangateOpenCellLibrary_slow_conditional.v", 1662: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\sregs_reg[PIL][1]
    $setuphold( posedge CK:65562, posedge D:65562, limits: (0,1) );


"NangateOpenCellLibrary_slow_conditional.v", 1662: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\sregs_reg[PIL][1]
    $setuphold( posedge CK:67722, posedge D:67722, limits: (0,1) );


2


"NangateOpenCellLibrary_slow_conditional.v", 1662: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\sregs_reg[PIL][1]
    $setuphold( posedge CK:69406, posedge D:69406, limits: (0,1) );


"NangateOpenCellLibrary_slow_conditional.v", 1662: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\sregs_reg[PIL][1]
    $setuphold( posedge CK:75022, posedge D:75022, limits: (0,1) );


"NangateOpenCellLibrary_slow_conditional.v", 1662: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\sregs_reg[PIL][1]
    $setuphold( posedge CK:77182, posedge D:77182, limits: (0,1) );

3


"NangateOpenCellLibrary_slow_conditional.v", 1662: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\sregs_reg[PIL][1]
    $setuphold( posedge CK:78866, posedge D:78866, limits: (0,1) );


"NangateOpenCellLibrary_slow_conditional.v", 1662: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\sregs_reg[PIL][1]
    $setuphold( posedge CK:84482, posedge D:84482, limits: (0,1) );


"NangateOpenCellLibrary_slow_conditional.v", 1662: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\sregs_reg[PIL][1]
    $setuphold( posedge CK:86642, posedge D:86642, limits: (0,1) );

4


"NangateOpenCellLibrary_slow_conditional.v", 1662: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\sregs_reg[PIL][1]
    $setuphold( posedge CK:88326, posedge D:88326, limits: (0,1) );


"NangateOpenCellLibrary_slow_conditional.v", 1662: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\sregs_reg[PIL][1]
    $setuphold( posedge CK:93942, posedge D:93942, limits: (0,1) );

"NangateOpenCellLibrary_slow_conditional.v", 1662: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\sregs_reg[PIL][1]
    $setuphold( posedge CK:96102, posedge D:96102, limits: (0,1) );

5


"NangateOpenCellLibrary_slow_conditional.v", 1662: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\sregs_reg[PIL][1]
    $setuphold( posedge CK:97786, posedge D:97786, limits: (0,1) );


"NangateOpenCellLibrary_slow_conditional.v", 1662: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\sregs_reg[PIL][1]
    $setuphold( posedge CK:103402, posedge D:103402, limits: (0,1) );


"NangateOpenCellLibrary_slow_conditional.v", 1662: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\sregs_reg[PIL][1]
    $setuphold( posedge CK:105562, posedge D:105562, limits: (0,1) );

6


"NangateOpenCellLibrary_slow_conditional.v", 1662: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\sregs_reg[PIL][1]
    $setuphold( posedge CK:107246, posedge D:107246, limits: (0,1) );


"NangateOpenCellLibrary_slow_conditional.v", 1662: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\sregs_reg[PIL][1]
    $setuphold( posedge CK:112862, posedge D:112862, limits: (0,1) );


"NangateOpenCellLibrary_slow_conditional.v", 1662: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\sregs_reg[PIL][1]
    $setuphold( posedge CK:115022, posedge D:115022, limits: (0,1) );

7


"NangateOpenCellLibrary_slow_conditional.v", 1662: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\sregs_reg[PIL][1]
    $setuphold( posedge CK:116706, posedge D:116706, limits: (0,1) );


"NangateOpenCellLibrary_slow_conditional.v", 1662: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\sregs_reg[PIL][1]
    $setuphold( posedge CK:122322, posedge D:122322, limits: (0,1) );


"NangateOpenCellLibrary_slow_conditional.v", 1662: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\sregs_reg[PIL][1]
    $setuphold( posedge CK:124482, posedge D:124482, limits: (0,1) );

8


"NangateOpenCellLibrary_slow_conditional.v", 1662: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\sregs_reg[PIL][1]
    $setuphold( posedge CK:126166, posedge D:126166, limits: (0,1) );


"NangateOpenCellLibrary_slow_conditional.v", 1662: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\sregs_reg[PIL][1]
    $setuphold( posedge CK:131782, posedge D:131782, limits: (0,1) );


"NangateOpenCellLibrary_slow_conditional.v", 1662: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\sregs_reg[PIL][1]
    $setuphold( posedge CK:133942, posedge D:133942, limits: (0,1) );

9


"NangateOpenCellLibrary_slow_conditional.v", 1662: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\sregs_reg[PIL][1]
    $setuphold( posedge CK:135626, posedge D:135626, limits: (0,1) );

Math Test


"NangateOpenCellLibrary_slow_conditional.v", 1662: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\sregs_reg[PIL][1]
    $setuphold( posedge CK:140958, posedge D:140958, limits: (0,1) );


"NangateOpenCellLibrary_slow_conditional.v", 1662: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\sregs_reg[PIL][1]
    $setuphold( posedge CK:150402, posedge D:150402, limits: (0,1) );


"NangateOpenCellLibrary_slow_conditional.v", 1662: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\sregs_reg[PIL][1]
    $setuphold( posedge CK:152846, posedge D:152846, limits: (0,1) );

25


"NangateOpenCellLibrary_slow_conditional.v", 1662: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\sregs_reg[PIL][1]
    $setuphold( posedge CK:155426, posedge D:155426, limits: (0,1) );

Hello


"NangateOpenCellLibrary_slow_conditional.v", 1662: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\sregs_reg[PIL][1]
    $setuphold( posedge CK:158830, posedge D:158830, limits: (0,1) );

159652 NS
Assertion FAILURE at 159652 NS in design unit TESTMOD(BEHAV) from process /TBLEON/TB/TESTMOD0/ERRMODE:
    "processor in error mode!"
 tbench/testmod.vhd(152):             assert  to_x01(error) = '1' report "processor in error mode!"
(simv): Simulation complete, time is 159652 (1 NS).

DFF_X2 \sregs_reg[PIL][1] ( .D(n4388), .CK(\iuo[DEBUG][CLK] ), .Q(n11598),
.QN(n3726) );


NangateOpenCellLibray_slow_conditional.v
Code: 
primitive seq16 (IQ, nextstate, CK, NOTIFIER);
  output IQ;
  input nextstate;
  input CK;
  input NOTIFIER;
  reg IQ;

  table
// nextstate          CK    NOTIFIER     : @IQ :          IQ
           0           r           ?       : ? :           0;
           1           r           ?       : ? :           1;
           0           *           ?       : 0 :           0; // reduce pessimism
           1           *           ?       : 1 :           1; // reduce pessimism
           *           ?           ?       : ? :           -; // Ignore all edges on nextstate
           ?           f           ?       : ? :           -; // Ignore non-triggering clock edge
           ?           ?           *       : ? :           x; // Any NOTIFIER change
  endtable
endprimitive

module DFF_X2 (CK, D, Q, QN);

  input CK;
  input D;
  output Q;
  output QN;
  reg NOTIFIER;

  seq16(IQ, nextstate, CK, NOTIFIER);
  not(IQN, IQ);
  buf(Q, IQ);
  buf(QN, IQN);
  buf(nextstate, D);

 specify
    (posedge CK => (Q +: D)) = (0.1, 0.1);
    (posedge CK => (QN -: D)) = (0.1, 0.1);

    $width(negedge CK, 0.1, 0, NOTIFIER);
    $width(posedge CK, 0.1, 0, NOTIFIER);
    $setuphold(posedge CK, negedge D, 0.1, 0.1, NOTIFIER);
[B][I]    $setuphold(posedge CK, posedge D, 0.1, 0.1, NOTIFIER);[/I][/B] ------>1662
    $width(negedge D, 0.1, 0, NOTIFIER);
    $width(posedge D, 0.1, 0, NOTIFIER);
  endspecify

endmodule
 

I've mentioned before that there is something suspicious about the clock and data for that register switching at exactly the same instant. I think you need to look at the simulation waveforms for that specific register and how the data and clock are generated to it, and also look in the SDF to make sure that all the timing arcs are covered.

It seems odd to me that the setuphold limit is 0,1 which is far as I can discern from the documentation would mean 0 setup and 1 hold, but I have no clue what the units are in (ps, ns, ?). Are you sure you aren't running your simulation with a timescale that is wrong and it's rounding everything to the nearest 1 ns or something?

Beyond that I won't even attempt to help further, as you never seem to give enough details without having to pry it out of you piece by piece.
 

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