Multiplication delay in Altera stratixII !!!

[icoin13]

SA

I'm trying to implement the digital signal processing of a gsm receiver on alterga stratixII fpga and this require to many multipication operation, and I want to know how many clock cycles delay should I expect of 20bit*20bit multiply operation? and if i want to multiply two arrays each of size 20*24 ( 20 element 24-bit each ) could I multiply the whole two array directly or element by element ?

thanks

 

[FvM]

You can refer to the Performance chapter from Startix II device manual. It says 250 MHz 36x36 multiply in one clock cycle or 410 MHz pipelined. For matrix multiply, refer to numerical mathematics literature.