Multiclock design(Argent)

[ssudhasa]

Hi, I have a question.

CLKA = 2 × CLKB

Signal in CLKA domain is active for 2 CLKA cycle.

At clock domain crossing we have used 2 bit synthronizer,
At synthronizer output, how many CLKB cycles it will have . ??

options:
(1) 1
(2) 2
(3) 3

And Also , for this MCD scenario, 2 bit synthronizer is sufficient?

Thanks in Anticipation!!

 

[ssudhasa]

Hi Please help.