[moved] how to encrypt part of the verilog code by using 1735 supported pragmas ?

[anilineda]

Hello,

There is a good news that vivado 2016.4 now support version 2 ieee standard encryption. I succesfully encrypted (.v) files by using the command as shown below in tcl console of vivado:

encrypt -key <path to public key in vivado install dir> -lang verilog <design>.v -ext .vp

the above command encrypt entire code but,
my question is, how to encrypt only some part of the code by writing 1735 supported pragma envelopes and also how to embed keys directly inside the code itself without using "-key" option.

please someone help me with the syntax and some reference.


Regards,
Anil

 

[dave_59]

Re: how to encrypt part of the verilog code by using 1735 supported pragmas ?

Check the section Encrypting IP in Vivado in the document Vivado Design Suite User Guide: Creating and Packaging Custom IP .

 

[anilineda]

Re: how to encrypt part of the verilog code by using 1735 supported pragmas ?

thank you so much. This is what i am looking for.
one more thing is, Till now we usually deliver the netlist file to our customers but for the first time we are thinking of providing them an encrypted RTL (made with ieee standard) . what would you like to say on this ? Is ieee 1735 will create any headaches of exposing the code. ?

 

[dave_59]

Re: how to encrypt part of the verilog code by using 1735 supported pragmas ?

Just make sure your code is thoroughly tested on the tools your customers plan on using(simulation and synthesis). It will be very difficult for them to debug it.

 

[vpopli]

Re: how to encrypt part of the verilog code by using 1735 supported pragmas ?

IP author can encrypt part of IP by enclosing that part of code in protect directives. https://ipencrypter.com provides information and tools for IP encryption.

<verilog_code_not_to_encrypt>
`pragma protect version=2
`pragma protect author="Author name", author_info="Author info"
`pragma protect data_method="aes128-cbc"
... more protect directives ...

`pragma protect begin
<verilog_code_to_encrypt>
`pragma protect end

<rest_of_verilog_code_not_to_encrypt>