Junus2012
Advanced Member level 5
Dear friends,
I started to work with ModGen to implement circuit layout, the tools is really healpful and can save a lot of time to implement complicated matched array,
I started the test with simple two transistors pairs as shown below, I followed all the steps from Cadence to generate the layout model, but unfortunately when it comes it has missing connections, for example the connection to the gates or to the upper source transistors are missing, although Cadence is recognizing the connection
Do you have please an idea about such problem
I started to work with ModGen to implement circuit layout, the tools is really healpful and can save a lot of time to implement complicated matched array,
I started the test with simple two transistors pairs as shown below, I followed all the steps from Cadence to generate the layout model, but unfortunately when it comes it has missing connections, for example the connection to the gates or to the upper source transistors are missing, although Cadence is recognizing the connection
Do you have please an idea about such problem